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Efficient approximation algorithms for floorplan area minimization

Published: 01 June 1996 Publication History
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References

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A. Aggarwal, M.M. Klawe, S. Moran, P. Shor and R. Wilber, "Geometric applications of a matrix-searching algorithm," Algorithmica, vol. 2, 1987, pp. 195-208.
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A. Aggarwal, B. Schieber and T. Tokuyama, "Finding a minimum weight k-link path in graphs with Monge property and applications," Proc. 9th Annual A CM Symp. on Computational Geometry, 1993, pp. 189-197.
[3]
E.L. Lawler, Combinatorial Optimization: Networks and Matroids. Holt, Rinehart and Winston, 1979.
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T. Lengauer and R. Muller, "A robust framework for hierarchical floorplanning with integrated global wiring," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1990, pp. 148-151.
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R.H.J.M. Otten, "Automatic floorplan design," Proc. 19th A CM/IEEE Design Automation Conf., 1982, pp. 261-267.
[6]
P. Pan and C.L. Liu, "Area minimization for floorplans," IEEE Trans. on Computer-Aided Design, vol. 14, no. 1, 1995, pp. 123-132.
[7]
M. Pedram and B. Preas, "A hierarchical floorplanning approach," Proc. IEEE Int'l Conf. on Computer Design, 1990, pp. 332-338.
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B. Schieber, "Computing a minimum-weight k-link path in graphs with the concave Monge property," Proc. 6th Annual A CM-SIAM Symp. on Disc. Algorithms, 1995, pp. 405-411.
[9]
T.-C. Wang and D.F. Wong, "Optimal floorplan area optimization," IEEE Trans. on Computer-Aided Design, vol. 11, no. 8, 1992, pp. 992-1002.
[10]
T.-C. Wang and D.F. Wong, "Graph-based techniques to speedup floorplan area optimization," Integration, the VLSI Journal, vol. 15, 1993, pp. 179-199.

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  • (1996)Minimizing chip-level simultaneous switching noise for high-performance microprocessor design1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 9610.1109/ISCAS.1996.542081(544-547)Online publication date: 1996

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cover image ACM Conferences
DAC '96: Proceedings of the 33rd annual Design Automation Conference
June 1996
839 pages
ISBN:0897917790
DOI:10.1145/240518
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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June 3 - 7, 1996
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  • (1996)Minimizing chip-level simultaneous switching noise for high-performance microprocessor design1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 9610.1109/ISCAS.1996.542081(544-547)Online publication date: 1996

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