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On static compaction of test sequences for synchronous sequential circuits

Published: 01 June 1996 Publication History
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References

[1]
R.K. Roy, T. M. Niermann, J. H. Patel, J. A. Abraham and R. A. Saleh, "Compaction of ATPG-Generated Test Sequences for Sequential Circuits", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1988, pp. 382-385.
[2]
B. So, "Time-Efficient Automatic Test Pattern Generation Systems", Ph.D. Thesis, EE Dept., Univ. of Wisconsin at Madison, 1994.
[3]
I. Pomeranz and S. M. Reddy, "On Generating Compact Test Sequences for Synchronous Sequential Circuits", EURO-DAC '95, Sept. 1995.
[4]
T. E Kelsey and K. K. Saluja, "Fast Test Generation for Sequential Circuits", Intl. Conf. Comp. Aided Design, Nov. 1989, pp. 354-357.
[5]
T. Niermann and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits", European Design Autom. Conf., 1991, pp. 214-218.
[6]
I. Pomeranz and S. M. Reddy, "LOCSTEP: A Logic Simulation Based Test Generation Procedure", 25th Fault-Tolerant Computing Symp., June 1995, pp. 110-119.
[7]
D.G. Saab, Y. G. Saab and J. A. Abraham, "CRIS: A Test Cultivation Program for Sequential VLSI Circuits", Intl. Conf. Computer-Aided Design, Nov. 1992, pp. 216-219.
[8]
E.M. Rudnick, J. H. Patel, G. S. Greenstein and T. M. Niermann, "Sequential Circuit Test Generation in a Genetic Algorithm Framework", in Proc. Design Autom. Conf., June 1994, pp. 698-704.
[9]
M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
[10]
W-T. Cheng and T. J. Chakraborty, "Gentest: An Automatic Test Generation System for Sequential Circuits", IEEE Computer, April 1989, pp. 43-49.

Cited By

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  • (2020)Broad-Brush Compaction for Sequential Test GenerationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.299209728:8(1940-1944)Online publication date: Aug-2020
  • (2016)Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching ActivityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251293135:10(1755-1762)Online publication date: 1-Oct-2016
  • (2015)FOLDACM Transactions on Design Automation of Electronic Systems10.1145/276445520:4(1-19)Online publication date: 28-Sep-2015
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    cover image ACM Conferences
    DAC '96: Proceedings of the 33rd annual Design Automation Conference
    June 1996
    839 pages
    ISBN:0897917790
    DOI:10.1145/240518
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 June 1996

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    June 3 - 7, 1996
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    DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;
    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2020)Broad-Brush Compaction for Sequential Test GenerationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.299209728:8(1940-1944)Online publication date: Aug-2020
    • (2016)Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching ActivityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251293135:10(1755-1762)Online publication date: 1-Oct-2016
    • (2015)FOLDACM Transactions on Design Automation of Electronic Systems10.1145/276445520:4(1-19)Online publication date: 28-Sep-2015
    • (2015)A Generalized Definition of Unnecessary Test Vectors in Functional Test SequencesACM Transactions on Design Automation of Electronic Systems10.1145/269985320:2(1-13)Online publication date: 2-Mar-2015
    • (2015)A definition of the number of detections for faults with single tests in a compact scan-based test set2015 IEEE 33rd VLSI Test Symposium (VTS)10.1109/VTS.2015.7116302(1-6)Online publication date: Apr-2015
    • (2015)Test vector omission with minimal sets of simulated faults2015 IEEE 33rd VLSI Test Symposium (VTS)10.1109/VTS.2015.7116297(1-6)Online publication date: Apr-2015
    • (2015)Improving the accuracy of defect diagnosis by considering reduced diagnostic information2015 IEEE 33rd VLSI Test Symposium (VTS)10.1109/VTS.2015.7116270(1-6)Online publication date: Apr-2015
    • (2015)Test Compaction by Sharing of Functional Test Sequences Among Logic BlocksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.238260923:12(3006-3014)Online publication date: Dec-2015
    • (2015)On test program compaction2015 20th IEEE European Test Symposium (ETS)10.1109/ETS.2015.7138771(1-6)Online publication date: May-2015
    • (2014)A Cube-Aware Compaction Method for Scan ATPGProceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.24(98-103)Online publication date: 5-Jan-2014
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