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Low power 3-D stacking multimedia platform with reconfigurable memory architecture

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Yi-Fa SunAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 311 - 312

https://doi.org/10.1145/2483028.2483117

Published: 02 May 2013 Publication History

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Abstract

In this paper, a low power and high performance three-dimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL) simulation, there is a 54% performance speedup compared with the former 2-D architecture for certain multimedia applications. This chip is fabricated in TSMC 90nm generic CMOS technology. The area of 2D-PAC is about 7880 x 7880 μm2 and the SRAM layer is about 3880 x 3880 μm2. Both layers are combined with 1,886 TSVs.

References

[1]

Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, and An-Yeu Wu, "Overview of ITRI PAC project -- from VLIW DSP processor to multicore computing platform," in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 188--191, Apr. 2008

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[2]

Y. F. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan, and M.J. Irwin, "Design Space Exploration for 3-D Cache," IEEE Transactions on Very Large Scale Integration Systems, pp. 444--455, Apr. 2008.

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[3]

A. Richard, D. Milojevic, F. Robert, A. Bartzas, A. Papanikolaou, K. Siozios, and D. Soudris, "Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's," in Proc. Architecture of Computing Systems (ARCS), pp. 1--6, Feb. 2010

Google Scholar

[4]

Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin, "Stacking Memory Architecture Exploration for Three-Dimensional Integrated Circuit in 3-D PAC," in Proc. IEEE International SoC Conference, pp. 317--321, Sep. 2012

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Index Terms

Low power 3-D stacking multimedia platform with reconfigurable memory architecture
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
    2. Parallel architectures

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Information & Contributors

Information

Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2013

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GLSVLSI'13

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SIGDA

GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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