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BitWeaving: fast scans for main memory data processing

Published: 22 June 2013 Publication History

Abstract

This paper focuses on running scans in a main memory data processing system at "bare metal" speed. Essentially, this means that the system must aim to process data at or near the speed of the processor (the fastest component in most system configurations). Scans are common in main memory data processing environments, and with the state-of-the-art techniques it still takes many cycles per input tuple to apply simple predicates on a single column of a table. In this paper, we propose a technique called BitWeaving that exploits the parallelism available at the bit level in modern processors. BitWeaving operates on multiple bits of data in a single cycle, processing bits from different columns in each cycle. Thus, bits from a batch of tuples are processed in each cycle, allowing BitWeaving to drop the cycles per column to below one in some case. BitWeaving comes in two flavors: BitWeaving/V which looks like a columnar organization but at the bit level, and BitWeaving/H which packs bits horizontally. In this paper we also develop the arithmetic framework that is needed to evaluate predicates using these BitWeaving organizations. Our experimental results show that both these methods produce significant performance benefits over the existing state-of-the-art methods, and in some cases produce over an order of magnitude in performance improvement.

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  • (2024)SFVInt: Simple, Fast and Generic Variable-Length Integer Decoding using Bit Manipulation InstructionsProceedings of the 20th International Workshop on Data Management on New Hardware10.1145/3662010.3663439(1-9)Online publication date: 10-Jun-2024
  • (2024)SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658485(1-6)Online publication date: 23-Jun-2024
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    cover image ACM Conferences
    SIGMOD '13: Proceedings of the 2013 ACM SIGMOD International Conference on Management of Data
    June 2013
    1322 pages
    ISBN:9781450320375
    DOI:10.1145/2463676
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 22 June 2013

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    Author Tags

    1. analytics
    2. bit-parallel
    3. indexing
    4. intra-cycle parallelism
    5. storage organization

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    SIGMOD '13 Paper Acceptance Rate 76 of 372 submissions, 20%;
    Overall Acceptance Rate 785 of 4,003 submissions, 20%

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    Cited By

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    • (2024)SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658485(1-6)Online publication date: 23-Jun-2024
    • (2024)LeCo: Lightweight Compression via Learning Serial CorrelationsProceedings of the ACM on Management of Data10.1145/36393202:1(1-28)Online publication date: 26-Mar-2024
    • (2024)Cabin: A Compressed Adaptive Binned Scan IndexProceedings of the ACM on Management of Data10.1145/36393122:1(1-26)Online publication date: 26-Mar-2024
    • (2024)SIMDified Data Processing - Foundations, Abstraction, and Advanced TechniquesCompanion of the 2024 International Conference on Management of Data10.1145/3626246.3654694(613-621)Online publication date: 9-Jun-2024
    • (2024)Hardware and Software Co-Design for Optimized Decoding Schemes and Application Mapping in NVM Compute-in-Memory ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344721643:11(3744-3755)Online publication date: Nov-2024
    • (2024)Search-in-Memory: Reliable, Versatile, and Efficient Data Matching in SSD’s NAND Flash Memory Chip for Data Indexing AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344370243:11(3864-3875)Online publication date: Nov-2024
    • (2024)REGER: Reordering Time Series Data for Regression Encoding2024 IEEE 40th International Conference on Data Engineering (ICDE)10.1109/ICDE60146.2024.00100(1242-1254)Online publication date: 13-May-2024
    • (2024)Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58291.2024.00024(99-114)Online publication date: 24-Jun-2024
    • (2023)SmartLite: A DBMS-Based Serving System for DNN Inference in Resource-Constrained EnvironmentsProceedings of the VLDB Endowment10.14778/3632093.363209517:3(278-291)Online publication date: 1-Nov-2023
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