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A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Authors:

Alessandro Antonio Nacci,

Francesco Bruschi,

Donatella Sciuto,

David AtienzaAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 52, Pages 1 - 6

https://doi.org/10.1145/2463209.2488797

Published: 29 May 2013 Publication History

Abstract

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

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Cited By

Del Sozzo EConficconi DSano K(2024)Across Time and Space: Senju’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/363492017:2(1-33)Online publication date: 30-Apr-2024
https://dl.acm.org/doi/10.1145/3634920
Reggiani EDel Sozzo EConficconi DNatale GMoroni CSantambrogio M(2021)Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL ComponentsACM Transactions on Reconfigurable Technology and Systems10.1145/346147814:3(1-33)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3461478
Wang JKang YLi YWu WLiu SWang L(2021)Hexagonal Tiling based Multiple FPGAs Stencil Computation Acceleration and Optimization Methodology2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom)10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00101(697-705)Online publication date: Sep-2021
https://doi.org/10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00101
Show More Cited By

Index Terms

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
2. Theory of computation
  1. Models of computation
    1. Concurrency
      1. Parallel computing models

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Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

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DAC '13

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Del Sozzo EConficconi DSano K(2024)Across Time and Space: Senju’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/363492017:2(1-33)Online publication date: 30-Apr-2024
https://dl.acm.org/doi/10.1145/3634920
Reggiani EDel Sozzo EConficconi DNatale GMoroni CSantambrogio M(2021)Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL ComponentsACM Transactions on Reconfigurable Technology and Systems10.1145/346147814:3(1-33)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3461478
Wang JKang YLi YWu WLiu SWang L(2021)Hexagonal Tiling based Multiple FPGAs Stencil Computation Acceleration and Optimization Methodology2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom)10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00101(697-705)Online publication date: Sep-2021
https://doi.org/10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00101
Koraei MFatemi S(2021)SASIAF, A Scalable Accelerator for Seismic Imaging on Amazon AWS FPGAs2021 11th International Conference on Computer Engineering and Knowledge (ICCKE)10.1109/ICCKE54056.2021.9721464(352-357)Online publication date: 28-Oct-2021
https://doi.org/10.1109/ICCKE54056.2021.9721464
Yantır HEltawil ASalama K(2020)Efficient Acceleration of Stencil Applications through In-Memory ComputingMicromachines10.3390/mi1106062211:6(622)Online publication date: 26-Jun-2020
https://doi.org/10.3390/mi11060622
Du CYamaguchi Y(2020)High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth MemoryElectronics10.3390/electronics90812759:8(1275)Online publication date: 8-Aug-2020
https://doi.org/10.3390/electronics9081275
Koraei MFatemi OJahre M(2019)DCMIACM Transactions on Architecture and Code Optimization10.1145/335281316:4(1-24)Online publication date: 11-Oct-2019
https://dl.acm.org/doi/10.1145/3352813
Nabi SVanderbauwhede W(2019)Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2019.00024(87-90)Online publication date: May-2019
https://doi.org/10.1109/IPDPSW.2019.00024
Castano-Londono LAlzate Anzola CMarquez-Viloria DGallo GOsorio G(2019)Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis ToolApplied Computer Sciences in Engineering10.1007/978-3-030-31019-6_5(52-63)Online publication date: 9-Oct-2019
https://doi.org/10.1007/978-3-030-31019-6_5
Reggiani ENatale GMoroni CSantambrogio M(2018)An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2018.00026(115-122)Online publication date: May-2018
https://doi.org/10.1109/IPDPSW.2018.00026
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