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A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

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Stephen KosonockyAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 167 - 172

https://doi.org/10.1145/2333660.2333703

Published: 30 July 2012 Publication History

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Abstract

This paper explores the benefits of splitting a monolithic power gate transistor into parallel, independently controlled, variable weighted power gates to provide programmable post-fabrication power grid resistance. This power gate topology creates energy saving opportunities by providing adjustable localized voltages during active modes and reducing leakage current in idle blocks while retaining data. Measurements show over 30% active energy savings per operation and 90% savings in idle current with retention. A modeling flow for a resistive power grid was also developed that demonstrates the effectiveness of this approach in a Bulldozer processor core.

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Cited By

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Wang YLin XPedram MCavallaro JZhang TJones ALi H(2014)Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power railsProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591585(323-328)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591585
Calhoun BCraig K(2013)Flexible on-chip power delivery for energy efficient heterogeneous systemsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488932(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488932

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A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs
1. Hardware

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Published In

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 30 July 2012

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ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Wang YLin XPedram MCavallaro JZhang TJones ALi H(2014)Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power railsProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591585(323-328)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591585
Calhoun BCraig K(2013)Flexible on-chip power delivery for energy efficient heterogeneous systemsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488932(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488932

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Flexible on-chip power delivery for energy efficient heterogeneous systems

Low power shift register using MTCMOS edge-trigger D flip flop transmission gate in sub-threshold region

A design of low swing and multi threshold voltage based low power 12T SRAM cell

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