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- Safieddine MZaraket FKanj REl-Zein ARoesner W(2019)Verification at RTL Using Separation of Design ConcernsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284858938:8(1529-1542)Online publication date: Aug-2019
- Leite MWehrmeister M(2018)System-level design based on UML/MARTE for FPGA-based embedded real-time systemsDesign Automation for Embedded Systems10.1007/s10617-016-9172-620:2(127-153)Online publication date: 19-Dec-2018
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