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Graph-coloring and treescan register allocation using repairing

Published: 09 October 2011 Publication History

Abstract

Graph coloring and linear scan are two appealing techniques for register allocation as the underlying formalism are extremely clean and simple. This paper advocates a decoupled approach that first lowers the register pressure by spilling variables, and then performs live ranges splitting/coalescing/coloring in a separate phase; this enables the design of simpler, cleaner, and more efficient register allocators.
This paper gives a new and more general approach to deal with register constraints. This approach called repairing does not require pre live range splitting and does not introduce additional spill code. It ignores register constraints during coloring/coalescing, and repairs violated constraints afterwards.
We applied this method to both graph based and scan based allocators into a decoupled approach. Here, the Iterated Register Coalescer (IRC) and a scan algorithm that uses Static Single Assignment (SSA) properties, the treescan. Moreover, this paper provides a survey on existing and new techniques of bias coloring during scan approaches.
Our experimental evaluation shows for the graph based approach, that we reduced the number of vertices (edges) in the interference graph by 26% (33%) without compromising the quality of the generated code. The treescan algorithm improved the compile time of the allocation process by 6.97x over IRC while providing comparable results for the quality of the generated code.

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  • (2021)Register AllocationSSA-based Compiler Design10.1007/978-3-030-80515-9_22(303-328)Online publication date: 12-Jun-2021
  • (2020)DRAGON: A Dynamic Distributed Resource Allocation Algorithm for Wireless NetworksIEEE Communications Letters10.1109/LCOMM.2020.298833424:8(1780-1783)Online publication date: Aug-2020
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cover image ACM Conferences
CASES '11: Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
October 2011
250 pages
ISBN:9781450307130
DOI:10.1145/2038698
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 October 2011

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Author Tags

  1. coalescing
  2. coloring
  3. fast register allocation
  4. register constraints
  5. ssa form

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  • Research-article

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ESWeek '11
ESWeek '11: Seventh Embedded Systems Week
October 9 - 14, 2011
Taipei, Taiwan

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

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  • (2022)Compilation of Parallel Data Access for Vector Processor in Radio Base StationsIEEE Embedded Systems Letters10.1109/LES.2021.308566414:1(11-14)Online publication date: Mar-2022
  • (2021)Register AllocationSSA-based Compiler Design10.1007/978-3-030-80515-9_22(303-328)Online publication date: 12-Jun-2021
  • (2020)DRAGON: A Dynamic Distributed Resource Allocation Algorithm for Wireless NetworksIEEE Communications Letters10.1109/LCOMM.2020.298833424:8(1780-1783)Online publication date: Aug-2020
  • (2019)DIAMOND: a distributed algorithm for vertex coloring problems and resource allocationIET Networks10.1049/iet-net.2018.52048:6(381-389)Online publication date: Nov-2019
  • (2018)Register optimizations for stencils on GPUsACM SIGPLAN Notices10.1145/3200691.317850053:1(168-182)Online publication date: 10-Feb-2018
  • (2018)Register optimizations for stencils on GPUsProceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3178487.3178500(168-182)Online publication date: 10-Feb-2018
  • (2018)Register allocation for Intel processor graphicsProceedings of the 2018 International Symposium on Code Generation and Optimization10.1145/3168806(352-364)Online publication date: 24-Feb-2018
  • (2018)Improving on Linear Scan Register AllocationInternational Journal of Automation and Computing10.1007/s11633-017-1100-015:2(228-238)Online publication date: 1-Apr-2018
  • (2017)Investigation on the Optimization for Storage Space in Register-SpillingCollaborate Computing: Networking, Applications and Worksharing10.1007/978-3-319-59288-6_63(627-633)Online publication date: 5-Jul-2017
  • (2015)Bytewise Register AllocationProceedings of the 18th International Workshop on Software and Compilers for Embedded Systems10.1145/2764967.2764971(22-27)Online publication date: 1-Jun-2015
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