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Performance bound analysis of analog circuits considering process variations

Authors:

Sheldon X.-D. Tan,

Guoyong ShiAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 310 - 315

https://doi.org/10.1145/2024724.2024799

Published: 05 June 2011 Publication History

Abstract

In this paper, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chip and manufacture processes. The new method applies a graph-based symbolic analysis and affine interval arithmetic to derive the variational transfer functions of analog circuits (linearized) with variational coefficients in forms of intervals. Then the frequency response bounds (maximum and minimum) are obtained by performing analysis of a finite number of transfer functions given by the Kharitonov's polynomial functions. We show that symbolic de-cancellation is critical for the affine interval analysis. The response bound given by the Kharitonov's functions are conservative given the correlations among coefficient intervals in transfer functions. Experimental results demonstrate the effectiveness of the proposed compared to the Monte Carlo method.

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Cited By

Chaudhuri JBhattacharya MChakrabarty K(2025)Enhancing Analog IC Security Using Randomized Obfuscation CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.346681044:3(867-881)Online publication date: Mar-2025
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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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New York, NY, United States

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Published: 05 June 2011

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chaudhuri JBhattacharya MChakrabarty K(2025)Enhancing Analog IC Security Using Randomized Obfuscation CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.346681044:3(867-881)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3466810
Ni LManoj P. D. SSong YGu CYu H(2016)A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248187335:6(1040-1051)Online publication date: Jun-2016
https://doi.org/10.1109/TCAD.2015.2481873
Zhong FLi BYuan B(2016)Circuit tolerance design by differential evolution with hybrid analysis method2016 Eighth International Conference on Advanced Computational Intelligence (ICACI)10.1109/ICACI.2016.7449806(74-78)Online publication date: Feb-2016
https://doi.org/10.1109/ICACI.2016.7449806
Li MHuang GWu XQian LZeng XZhou D(2016)A yield-enhanced global optimization methodology for analog circuit based on extreme value theoryScience China Information Sciences10.1007/s11432-015-0471-459:8Online publication date: 7-Jun-2016
https://doi.org/10.1007/s11432-015-0471-4
Minghua Li Zhaori Bi Zhou DZeng X(2015)Analog circuit performance bound estimation based on extreme value theory2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2015.7282062(1-4)Online publication date: Aug-2015
https://doi.org/10.1109/MWSCAS.2015.7282062
Aridhi HZaki MTahar S(2015)Fast statistical analysis of nonlinear analog circuits using model order reductionAnalog Integrated Circuits and Signal Processing10.1007/s10470-015-0588-x85:3(379-394)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s10470-015-0588-x
Manoj PYu HGu CZhuo CChang Y(2014)A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitterProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691506(696-701)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691506
Song YSai Manoj PYu HFettweis GNebel W(2014)Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variationsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616621(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616621
Kaergel MOlbrich MBarke EDavid EOrdonez Mde Azevedo RKinget P(2014)Simulation Based Verification with Range Based Signal Representations for Mixed-Signal SystemsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2661010(1-7)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1145/2660540.2661010
Manoj PYu HGu CZhuo C(2014)A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001428(696-701)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001428
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