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Lime: a Java-compatible and synthesizable language for heterogeneous architectures

Authors:

Joshua Auerbach,

David F. Bacon,

Rodric RabbahAuthors Info & Claims

ACM SIGPLAN Notices, Volume 45, Issue 10

Pages 89 - 108

https://doi.org/10.1145/1932682.1869469

Published: 17 October 2010 Publication History

Abstract

The halt in clock frequency scaling has forced architects and language designers to look elsewhere for continued improvements in performance. We believe that extracting maximum performance will require compilation to highly heterogeneous architectures that include reconfigurable hardware.

We present a new language, Lime, which is designed to be executable across a broad range of architectures, from FPGAs to conventional CPUs. We present the language as a whole, focusing on its novel features for limiting side-effects and integration of the streaming paradigm into an object- oriented language. We conclude with some initial results demonstrating applications running either on a CPU or co- executing on a CPU and an FPGA.

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Xiao YMicallef EButt AHofmann MAlston MGoldsmith MMerczynski-Hait ADeHon AFalsafi BFerdman MLu SWenisch T(2022)PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507740(933-945)Online publication date: 28-Feb-2022
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Liu XBuyya R(2020)Resource Management and Scheduling in Distributed Stream Processing SystemsACM Computing Surveys10.1145/335539953:3(1-41)Online publication date: 28-May-2020
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Index Terms

Lime: a Java-compatible and synthesizable language for heterogeneous architectures
1. Hardware
  1. Integrated circuits
    1. Logic circuits
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 45, Issue 10

OOPSLA '10

October 2010

957 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1932682

Issue’s Table of Contents

OOPSLA '10: Proceedings of the ACM international conference on Object oriented programming systems languages and applications
October 2010
984 pages
ISBN:9781450302036
DOI:10.1145/1869459
General Chairs:
William R. Cook
University of Texas at Austin
,
Siobhán Clarke
Trinity College Dublin
,
Program Chairs:
Martin Rinard
MIT
,
Kevin J. Sullivan
University of Virginia
,
Daniel H. Steinberg
Dim Sum Thinking Inc.

Copyright © 2010 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 October 2010

Published in SIGPLAN Volume 45, Issue 10

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Cited By

Fryer JGarcia P(2023)The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image ProcessingJournal of Signal Processing Systems10.1007/s11265-023-01885-595:10(1181-1201)Online publication date: 29-Jul-2023
https://doi.org/10.1007/s11265-023-01885-5
Xiao YMicallef EButt AHofmann MAlston MGoldsmith MMerczynski-Hait ADeHon AFalsafi BFerdman MLu SWenisch T(2022)PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507740(933-945)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507740
Liu XBuyya R(2020)Resource Management and Scheduling in Distributed Stream Processing SystemsACM Computing Surveys10.1145/335539953:3(1-41)Online publication date: 28-May-2020
https://dl.acm.org/doi/10.1145/3355399
Rodríguez ANavarro AAsenjo RCorbera FGran RSuárez DNunez-Yanez J(2020)Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platformThe Journal of Supercomputing10.1007/s11227-019-02935-176:6(4645-4665)Online publication date: 1-Jun-2020
https://dl.acm.org/doi/10.1007/s11227-019-02935-1
Rodríguez ANavarro AAsenjo RCorbera FGran RSuárez DNunez-Yanez J(2019)Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCsJournal of Systems Architecture10.1016/j.sysarc.2019.06.006Online publication date: Jun-2019
https://doi.org/10.1016/j.sysarc.2019.06.006
Wu SDong XZhang XZhu Z(2019)NoTThe Journal of Supercomputing10.1007/s11227-019-02749-175:7(3810-3841)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s11227-019-02749-1
Pauget BPearce DPotanin AKell SMarr S(2018)Towards compilation of an imperative language for FPGAsProceedings of the 10th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages10.1145/3281287.3281291(47-56)Online publication date: 4-Nov-2018
https://dl.acm.org/doi/10.1145/3281287.3281291
Li BTan KLuo LPeng YLuo RXu NXiong YCheng PChen EBarcellos MCrowcroft JVahdat AKatti S(2016)ClickNPProceedings of the 2016 ACM SIGCOMM Conference10.1145/2934872.2934897(1-14)Online publication date: 22-Aug-2016
https://dl.acm.org/doi/10.1145/2934872.2934897
Liu LLiu MWang CWang J(2016)Compile-Time Automatic Synchronization Insertion and Redundant Synchronization Elimination for GPU Kernels2016 IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS.2016.0112(826-834)Online publication date: Dec-2016
https://doi.org/10.1109/ICPADS.2016.0112
Mamaghani MSokolov DGarside J(2016)Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis2016 16th International Conference on Application of Concurrency to System Design (ACSD)10.1109/ACSD.2016.22(104-113)Online publication date: Jun-2016
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