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DART: a programmable architecture for NoC simulation on FPGAs

Authors:

Natalie Enright Jerger,

J. Gregory SteffanAuthors Info & Claims

NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Pages 145 - 152

https://doi.org/10.1145/1999946.1999970

Published: 01 May 2011 Publication History

Abstract

The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems [3]. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms---hence the study of new NoC designs can be very time-intensive. To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out in hardware on the FPGA like previous approaches [8, 6], our design virtualizes the NoC by mapping its components to a generic NoC simulation engine, composed of a fully-connected collection of fundamental components (e.g., routers and flit queues). This approach has two main advantages: (i) since FPGA implementation is decoupled it can simulate any NoC; and (ii) any NoC can be mapped to the engine without resynthe-sizing it, which can take time for a large FPGA design. We demonstrate that an implementation of DART can achieve over 100x speedup relative to a cycle-based software simulator, while maintaining the same level of simulation accuracy.

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Cited By

Asadi Y(2024)A comprehensive study and holistic review of empowering network-on-chip application mapping through machine learning techniquesDiscover Electronics10.1007/s44291-024-00027-w1:1Online publication date: 24-Oct-2024
https://doi.org/10.1007/s44291-024-00027-w
Muhsen YHusin NZolkepli MManshor NAl-Hchaimi A(2023)Evaluation of the Routing Algorithms for NoC-Based MPSoC: A Fuzzy Multi-Criteria Decision-Making ApproachIEEE Access10.1109/ACCESS.2023.331024611(102806-102827)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3310246
Prasad BParane KTalawar B(2021)FPGA friendly NoC simulation acceleration framework employing the hard blocksComputing10.1007/s00607-020-00901-xOnline publication date: 16-Jan-2021
https://doi.org/10.1007/s00607-020-00901-x
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Index Terms

DART: a programmable architecture for NoC simulation on FPGAs
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures

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Published In

cover image ACM Conferences

NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

May 2011

282 pages

ISBN:9781450307208

DOI:10.1145/1999946

General Chairs:
Radu Marculescu
CMU
,
Mike Kishinevsky
Intel
,
Program Chairs:
Ran Ginosar
Technion, Israel
,
Karam S. Chatha
Arizona State University

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 2011

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NOCS'11

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NOCS'11: International Symposium on Networks-on-Chips

May 1 - 4, 2011

Pennsylvania, Pittsburgh

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Overall Acceptance Rate 14 of 44 submissions, 32%

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Cited By

Asadi Y(2024)A comprehensive study and holistic review of empowering network-on-chip application mapping through machine learning techniquesDiscover Electronics10.1007/s44291-024-00027-w1:1Online publication date: 24-Oct-2024
https://doi.org/10.1007/s44291-024-00027-w
Muhsen YHusin NZolkepli MManshor NAl-Hchaimi A(2023)Evaluation of the Routing Algorithms for NoC-Based MPSoC: A Fuzzy Multi-Criteria Decision-Making ApproachIEEE Access10.1109/ACCESS.2023.331024611(102806-102827)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3310246
Prasad BParane KTalawar B(2021)FPGA friendly NoC simulation acceleration framework employing the hard blocksComputing10.1007/s00607-020-00901-xOnline publication date: 16-Jan-2021
https://doi.org/10.1007/s00607-020-00901-x
Xu ZChen YLing XGuan S(2019)Multi-applications mapping platform based on hardware and softwareProceedings of the 3rd International Conference on High Performance Compilation, Computing and Communications10.1145/3318265.3318267(128-132)Online publication date: 8-Mar-2019
https://dl.acm.org/doi/10.1145/3318265.3318267
Prabhu PParane KTalawar B(2019)High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs20th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2019.8697444(163-169)Online publication date: Mar-2019
https://doi.org/10.1109/ISQED.2019.8697444
Parane KPrabhu Prasad BTalawar B(2018)YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAsJournal of Circuits, Systems and Computers10.1142/S0218126619502025(1950202)Online publication date: 22-Nov-2018
https://doi.org/10.1142/S0218126619502025
Prabhu Prasad B M Parane KTalawar B(2018)YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.39(67-72)Online publication date: Jan-2018
https://doi.org/10.1109/VLSID.2018.39
Chaudhari ABraun M(2018)A Scalable FPGA Architecture for Flexible, Large-Scale, Real-Time RF Channel Emulation2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449390(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449390
Sangeetha GRadhakrishnan VPrasad PParane KTalawar B(2018)Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA2018 8th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2018.8703884(129-134)Online publication date: Dec-2018
https://doi.org/10.1109/ISED.2018.8703884
Jerger NKrishna TPeh L(2017)On-Chip Networks, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00772ED1V01Y201704CAC04012:3(1-210)Online publication date: 17-Jun-2017
https://doi.org/10.2200/S00772ED1V01Y201704CAC040
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