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Optimizing hybrid transactional memory: the importance of nonspeculative operations

Published: 04 June 2011 Publication History

Abstract

Transactional memory (TM) is a speculative shared-memory synchronization mechanism used to speed up concurrent programs. Most current TM implementations are software-based (STM) and incur noticeable overheads for each transactional memory access. Hardware TM proposals (HTM) address this issue but typically suffer from other restrictions such as limits on the number of data locations that can be accessed in a transaction.
In this paper, we present several new hybrid TM algorithms that can execute HTM and STM transactions concurrently and can thus provide good performance over a large spectrum of workloads. The algorithms exploit the ability of some HTMs to have both speculative and nonspeculative (nontransactional) memory accesses within a transaction to decrease the transactions' runtime overhead, abort rates, and hardware capacity requirements. We evaluate implementations of these algorithms based on AMD's Advanced Synchronization Facility, an x86 instruction set extension proposal that has been shown to provide a sound basis for HTM.

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Cited By

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  • (2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
  • (2021)FIRestarter: Practical Software Crash Recovery with Targeted Library-level Fault Injection2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN48987.2021.00048(363-375)Online publication date: Jun-2021
  • (2019)Leveraging hardware TM in HaskellProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295711(94-106)Online publication date: 16-Feb-2019
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cover image ACM Conferences
SPAA '11: Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
June 2011
404 pages
ISBN:9781450307437
DOI:10.1145/1989493
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 June 2011

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Cited By

View all
  • (2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
  • (2021)FIRestarter: Practical Software Crash Recovery with Targeted Library-level Fault Injection2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN48987.2021.00048(363-375)Online publication date: Jun-2021
  • (2019)Leveraging hardware TM in HaskellProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295711(94-106)Online publication date: 16-Feb-2019
  • (2019)The Case for Phase-Based Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286171230:2(459-472)Online publication date: 1-Feb-2019
  • (2018)Enhancing efficiency of hybrid transactional memory via dynamic data partitioning schemesProceedings of the 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing10.1109/CCGRID.2018.00020(51-61)Online publication date: 1-May-2018
  • (2018)Inherent limitations of hybrid transactional memoryDistributed Computing10.1007/s00446-017-0305-331:3(167-185)Online publication date: 1-Jun-2018
  • (2017)DyAdHyTMProceedings of the International Symposium on Memory Systems10.1145/3132402.3132442(327-336)Online publication date: 2-Oct-2017
  • (2017)A Template for Implementing Fast Lock-free Trees Using HTMProceedings of the ACM Symposium on Principles of Distributed Computing10.1145/3087801.3087834(293-302)Online publication date: 25-Jul-2017
  • (2017)Revisiting phased transactional memoryProceedings of the International Conference on Supercomputing10.1145/3079079.3079094(1-10)Online publication date: 14-Jun-2017
  • (2017)Managing Resource Limitation of Best-Effort HTMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.266841528:8(2299-2313)Online publication date: 1-Aug-2017
  • Show More Cited By

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