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Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)

Authors:

Joshua M. Levine,

Edward Stott,

George A. Constantinides,

Peter Y.K. CheungAuthors Info & Claims

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Page 284

https://doi.org/10.1145/1950413.1950482

Published: 27 February 2011 Publication History

Abstract

Literature suggests that timing performance degradation in VLSI could be a major concern in future process technologies. FPGAs are well suited to cope with this challenge, due to their flexibility at design-, manufacture- and run-time.

Existing timing measurement techniques allow for the measurement of delay while the circuit is not operating, and reliability techniques allow for the detection of faults as they occur in operating circuits. Neither allows for the health of an operating circuit to be measured. The ability to monitor the health of a system can provide an early warning of impending failure. This information will enable measures to reduce the impact of, or avoid altogether, the failure. A good indication of the degree of degradation in an operating circuit is the available timing slack in a combinatorial circuit path, between registers, while the circuit is operating at speed.

This work proposes a new time delay measurement technique that does not interfere with the circuit's normal operation. This is achieved by sweeping the phase of a secondary clock signal, driving additional shadow registers. These are connected to each circuit node to be measured, typically those on the most critical paths. The technique is able to measure the timing slack available in the circuit-under-test, while it is performing its usual function.

The technique is demonstrated using a 12-stage LUT chain, and on an 8-bit ripple-carry adder, implemented on an Altera Cyclone III FPGA. It is able to measure the timing slack with a best case resolution of 96ps. The additional circuitry has minimal overhead in terms of area, power consumption, and timing. The increase in circuit delay due to extra fan-out load was measured to be 0.25% in the first example circuit.

References

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Cited By

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Jiang WYu HZhang HShu YLi RChen JHa Y(2022)FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.314432130:4(502-514)Online publication date: Apr-2022
https://doi.org/10.1109/TVLSI.2022.3144321

Index Terms

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

February 2011

300 pages

ISBN:9781450305549

DOI:10.1145/1950413

General Chair:
John Wawrzynek
University of California, Berkeley, USA
,
Program Chair:
Katherine Compton
University of Wisconsin-Madison, USA

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Association for Computing Machinery

New York, NY, United States

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Published: 27 February 2011

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February 27 - March 1, 2011

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Jiang WYu HZhang HShu YLi RChen JHa Y(2022)FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.314432130:4(502-514)Online publication date: Apr-2022
https://doi.org/10.1109/TVLSI.2022.3144321

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References

Cited By

Index Terms

Recommendations

Sequential Large Multipliers on FPGAs

Area Minimization of Exclusive-OR Intensive Circuits in FPGAs

Digit-Serial Complex-Number Multipliers on FPGAs

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