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Functional unit level parallelism in RISC architecture

Published: 16 December 2009 Publication History

Abstract

This paper presents the design and implementation of RISC processor having five stages pipelined architecture. Functional unit parallelism is exploited through the implementation of pipelining in five stages of RISC processor. The hazards which come to life due to parallelism are data, structural, and control hazards. In order to achieve the true benefits of the parallelism through pipelining; these hazards must be properly handled. The data hazards are solved using bypassing in which we forward the required value of the operand to the succeeding instruction. Structural hazards are solved by implementing three port register file so that two operand reading and one register writing can be performed in parallel without degrading the performance. Control hazards arise from Branch, Jump and Call instructions. To solve these problems, we insert automated NOP in stage2, stage3 and stage4. The processor designed is a fully functional processor which can execute any program including jump statements, switch statements, loops and subroutines which are the basic ingredients of any computer program.

References

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B. B. Bray, Microprocessor Based Assembly Language
[2]
David A. Patterson and Carlo H. Sequin. A Reduced Instruction Set VLSI Computer, University of California
[3]
Floyd, Fundametals of Digital Electronics
[4]
Morris Mano (2000), Digital Logic & Computer Design
[5]
Manolis katevenis, Distributed and Parallel Processing, RISC Architectures (ch20)
[6]
Michael J. Flynn. Towards Better Instruction Set, Stanford University, Stanford, CA and Palyn associated, CA
[7]
Samir Planitkar (1996), Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall.
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Sofiene Tahar and Ramaya Kumar. Formal Verification of Pipeline Conflicts in RISC processors.

Cited By

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  • (2020)Design and Implementation of 32-bit Functional Unit for RISC architecture applications2020 5th International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCS48716.2020.243545(46-48)Online publication date: Mar-2020

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FIT '09: Proceedings of the 7th International Conference on Frontiers of Information Technology
December 2009
446 pages
ISBN:9781605586427
DOI:10.1145/1838002
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • COMSATS Institute of Information Technology

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 December 2009

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Author Tags

  1. RISC
  2. parallelism etc
  3. pipelining

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  • (2020)Design and Implementation of 32-bit Functional Unit for RISC architecture applications2020 5th International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCS48716.2020.243545(46-48)Online publication date: Mar-2020

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