Designing working systems with imperfect chips

The design for manufacturing and yield (DFM&Y) is fast becoming an indispensable consideration in today's SoCs.

Most current flows only consider manufacturability and yield at the lowest levels: process, layout and circuit. As such, these metrics are treated as an afterthought. With advanced process nodes, it has become increasingly expensive --and soon prohibitive-- to guarantee bit level error free chips. The challenge now is to design reliable systems using chips that may have some faults. This has lead to approaches that consider DFM&Y at the system level where more benefit can be reaped, and to consider the problem across the design layers. Cross-layer approaches are increasingly employed to design for DFM&Y spanning from the application all the way to manufacturing. Various techniques are being explored today, and their effectiveness can be demonstrated on key applications including wireless, multimedia and imaging.