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10.1145/1854099.1854148acmotherconferencesArticle/Chapter ViewAbstractPublication PagessinConference Proceedingsconference-collections
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FPGA based programmable embedded intrusion detection system

Published: 07 September 2010 Publication History

Abstract

In this article, the design of a Field Programmable Gate Array (FPGA) based real time Intrusion Detection System (IDS) is presented. The embedded system first summarizes and normalizes the packets and then determines whether there is an attack or not using this summary according to the naive bayesian algorithm. The packet summaries which play an important role in the accurate classification of the packets include data such as the IP numbers of the packets, port numbers, protocol types and packet length. Real time Intrusion Detection System (IDS) was designed in the Altera Cyclone III based FPGA development environment and tested. As a result of the tests performed, appropriate results were obtained.

References

[1]
Das, A., Nuguyen, D., Zambreno, J., Memik, G., Choudhary, A., 2008. An FPGA-Based Network Intrusion Detection Architecture. IEEE Transaction on Information Forensics and Security, 3, 1, 118--132.
[2]
Katashita, T., Yamaguchi, Y., Maeda, A., Toda, K., 2007. FPGA- Based Intrusion Detection System for 10 Gigabit Ethernet, IEICE Transaction Information & System. E90-D, 12 1923--1931.
[3]
Kim, B.-K., Heo, Y.-J., Oh, J.-T., 2006, Design and Implementation of FPGA Based High-Performance Intrusion Detection System, Vol:3975, pp:724--725.
[4]
Amor, N. B., Benferhat, S., Elouedi, Z., 2004. Naïve Bayes vs Decision Trees in Intrusion Detection System, Proceedings of The ACM Symposium on Applied Computing, Nicosia, 420--424.
[5]
Hassan A. A., Elnakib A., Abo-Elsoud M., 2008, FPGA-Based Neuro Architecture Intrusion Detection, The proceeding of The International Conference on Computer Engineering & Systems, pp:268--273.
[6]
Tuncer T., 2010, Intrusion Detection System Designs For Computer Networks And Their Implementations In FPGA Environment, Phd. Thesis, Firat Universitiy.
[7]
Adrian P. Lauf, Richard A. Peters, and William H. Robinson, 2007, Embedded Intelligent Intrusion Detection: A Behavior-Based Approach, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07).
[8]
Altera.com, Access Date:01.01.2010.
[9]
Altera Corporation, 2007, Nios II Hardware Development Tutorial.

Cited By

View all
  • (2020)Configurable FPGA-Based Outlier Detection for Time Series Data2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS48704.2020.9184548(142-145)Online publication date: Aug-2020
  • (2017)Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded SystemsIEEE Transactions on Computers10.1109/TC.2016.256083966:1(163-177)Online publication date: 1-Jan-2017
  • (2011)Detection DoS Attack on FPGA Using Fuzzy Association RulesProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.171(1271-1276)Online publication date: 16-Nov-2011

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  1. FPGA based programmable embedded intrusion detection system

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    Published In

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    SIN '10: Proceedings of the 3rd international conference on Security of information and networks
    September 2010
    286 pages
    ISBN:9781450302340
    DOI:10.1145/1854099
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    • Microsoft: Microsoft
    • RFBR: Russian Foundation for Basic Research

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 07 September 2010

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    Author Tags

    1. embedded system
    2. intrusion detection system
    3. system on programmable chip

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    • Research-article

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    SIN '10
    Sponsor:
    • Microsoft
    • RFBR
    SIN '10: 3rd International Conference of Security of Information and Networks
    September 7 - 11, 2010
    Rostov-on-Don, Taganrog, Russian Federation

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    Overall Acceptance Rate 102 of 289 submissions, 35%

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    Cited By

    View all
    • (2020)Configurable FPGA-Based Outlier Detection for Time Series Data2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS48704.2020.9184548(142-145)Online publication date: Aug-2020
    • (2017)Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded SystemsIEEE Transactions on Computers10.1109/TC.2016.256083966:1(163-177)Online publication date: 1-Jan-2017
    • (2011)Detection DoS Attack on FPGA Using Fuzzy Association RulesProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.171(1271-1276)Online publication date: 16-Nov-2011

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