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Dynamically replicated memory: building reliable systems from nanoscale resistive memories

Authors:

Edmund B. Nightingale,

Thomas MoscibrodaAuthors Info & Claims

ACM SIGPLAN Notices, Volume 45, Issue 3

Pages 3 - 14

https://doi.org/10.1145/1735971.1736023

Published: 13 March 2010 Publication History

Abstract

DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must de- commission pages of PCM when the first bit fails.

This paper presents dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.

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Cited By

Escuin CIbáñez PNavarro DMonreal TLlabería JViñals V(2023)L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetimePLOS ONE10.1371/journal.pone.027834618:2(e0278346)Online publication date: 7-Feb-2023
https://doi.org/10.1371/journal.pone.0278346
Eom YKim CChoi J(2023)Exploiting Non-Volatile Memories to Improve Reliability of Processing Element for Railway Electronic Safety SystemsJournal of Electrical Engineering & Technology10.1007/s42835-022-01370-218:4(3301-3309)Online publication date: 20-Jan-2023
https://doi.org/10.1007/s42835-022-01370-2
Urquijo GVoelckers KMeyer ABellinger CAsadinia M(2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
https://doi.org/10.1007/978-3-031-47457-6_34
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Index Terms

Dynamically replicated memory: building reliable systems from nanoscale resistive memories
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 45, Issue 3

ASPLOS '10

March 2010

399 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1735971

Issue’s Table of Contents

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems
March 2010
422 pages
ISBN:9781605588391
DOI:10.1145/1736020
General Chair:
James C. Hoe
Carnegie Mellon University, USA
,
Program Chair:
Vikram S. Adve
University of Illinois at Urbana-Champaign, USA

Copyright © 2010 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 March 2010

Published in SIGPLAN Volume 45, Issue 3

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Cited By

Escuin CIbáñez PNavarro DMonreal TLlabería JViñals V(2023)L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetimePLOS ONE10.1371/journal.pone.027834618:2(e0278346)Online publication date: 7-Feb-2023
https://doi.org/10.1371/journal.pone.0278346
Eom YKim CChoi J(2023)Exploiting Non-Volatile Memories to Improve Reliability of Processing Element for Railway Electronic Safety SystemsJournal of Electrical Engineering & Technology10.1007/s42835-022-01370-218:4(3301-3309)Online publication date: 20-Jan-2023
https://doi.org/10.1007/s42835-022-01370-2
Urquijo GVoelckers KMeyer ABellinger CAsadinia M(2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
https://doi.org/10.1007/978-3-031-47457-6_34
Khan MGhosh S(2021)Comprehensive Study of Security and Privacy of Emerging Non-Volatile MemoriesJournal of Low Power Electronics and Applications10.3390/jlpea1104003611:4(36)Online publication date: 24-Sep-2021
https://doi.org/10.3390/jlpea11040036
Cai MHuang H(2021)A survey of operating system support for persistent memoryFrontiers of Computer Science10.1007/s11704-020-9395-315:4Online publication date: 11-Feb-2021
https://doi.org/10.1007/s11704-020-9395-3
Lu SLi HMiyase KHsu CSun C(2021)Fault-Aware Dependability Enhancement Techniques for Phase Change MemoryJournal of Electronic Testing10.1007/s10836-021-05961-1Online publication date: 14-Aug-2021
https://doi.org/10.1007/s10836-021-05961-1
Powers BTench DBerger EMcGregor AMcKinley KFisher K(2019)Mesh: compacting memory management for C/C++ applicationsProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3314221.3314582(333-346)Online publication date: 8-Jun-2019
https://dl.acm.org/doi/10.1145/3314221.3314582
Kwon TImran MYou JYang J(2018)Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342272(1610-1615)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342272
Ho CLiu YChang YKuo T(2017)Antiwear Leveling Design for SSDs With Hybrid ECC CapabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.258931825:2(488-501)Online publication date: 1-Feb-2017
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Zhao JXu CZhang TXie Y(2016)BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile MemoriesJournal of Computer Science and Technology10.1007/s11390-016-1609-731:1(20-35)Online publication date: 8-Jan-2016
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