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Scan line array processors for image computation

Author:

A. L. FisherAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 14, Issue 2

Pages 338 - 345

https://doi.org/10.1145/17356.17396

Published: 01 May 1986 Publication History

Abstract

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

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Cited By

Alnuweiri HPrasanna Kumar V(2005)Parallel convexity algorithms for digitized images on a linear array of processorsAlgorithms10.1007/3-540-52921-7_89(397-406)Online publication date: 4-Jun-2005
https://doi.org/10.1007/3-540-52921-7_89
Magnusson ASillitoe I(2004)Constructive evolution of morphological filters for high-speed embedded image processing2004 IEEE International Conference on Systems, Man and Cybernetics (IEEE Cat. No.04CH37583)10.1109/ICSMC.2004.1400794(3022-3027)Online publication date: 2004
https://doi.org/10.1109/ICSMC.2004.1400794
Mozef EWeber SJaber JTisserand E(1996)Parallel architecture dedicated to connected component analysisProceedings of 13th International Conference on Pattern Recognition10.1109/ICPR.1996.547655(699-703 vol.4)Online publication date: 1996
https://doi.org/10.1109/ICPR.1996.547655
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Scan line array processors for image computation

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 14, Issue 2

Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

May 1986

429 pages

ISSN:0163-5964

DOI:10.1145/17356

Editor:
Hideo Aiso

Issue’s Table of Contents

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture
June 1986
454 pages
ISBN:081860719X
Chairman:
Hideo Aiso

Copyright © 1986 Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Published in SIGARCH Volume 14, Issue 2

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Cited By

Alnuweiri HPrasanna Kumar V(2005)Parallel convexity algorithms for digitized images on a linear array of processorsAlgorithms10.1007/3-540-52921-7_89(397-406)Online publication date: 4-Jun-2005
https://doi.org/10.1007/3-540-52921-7_89
Magnusson ASillitoe I(2004)Constructive evolution of morphological filters for high-speed embedded image processing2004 IEEE International Conference on Systems, Man and Cybernetics (IEEE Cat. No.04CH37583)10.1109/ICSMC.2004.1400794(3022-3027)Online publication date: 2004
https://doi.org/10.1109/ICSMC.2004.1400794
Mozef EWeber SJaber JTisserand E(1996)Parallel architecture dedicated to connected component analysisProceedings of 13th International Conference on Pattern Recognition10.1109/ICPR.1996.547655(699-703 vol.4)Online publication date: 1996
https://doi.org/10.1109/ICPR.1996.547655
Wills DLacy WLopez-Lagunas AMay PSmith STaha TBaker JCat HChai SCodrescu LCruz-Rivera JEble JGentile AHopper M(1996)Processing architectures for smart pixel systemsIEEE Journal of Selected Topics in Quantum Electronics10.1109/2944.5418722:1(24-34)Online publication date: Apr-1996
https://doi.org/10.1109/2944.541872
Helman DJáJá J(1995)Efficient Image Processing Algorithms on the Scan Line Array ProcessorIEEE Transactions on Pattern Analysis and Machine Intelligence10.1109/34.36815317:1(47-56)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1109/34.368153
Helman DJaja J(1993)Efficient Image Processing Algorithms on the Scan Line Array ProcessorProceedings of the 1993 International Conference on Parallel Processing - Volume 0310.1109/ICPP.1993.72(90-93)Online publication date: 16-Aug-1993
https://dl.acm.org/doi/10.1109/ICPP.1993.72
Alnuweiri HPrasanna V(1992)Parallel Architectures and Algorithms for Image Component LabelingIEEE Transactions on Pattern Analysis and Machine Intelligence10.1109/34.15990414:10(1014-1034)Online publication date: 1-Oct-1992
https://dl.acm.org/doi/10.1109/34.159904
Alnuweiri HPrasanna V(1991)Optimal geometric algorithms for digitized images on fixed-size linear arrays and scan-line arraysDistributed Computing10.1007/BF022597475:2(55-65)Online publication date: 1-Sep-1991
https://dl.acm.org/doi/10.1007/BF02259747
Dikaiakos MSteiglitz K(1991)Comparison of tree and straight-line clocking for long systolic arraysJournal of VLSI signal processing systems for signal, image and video technology10.1007/BF009254712:4(287-299)Online publication date: 1-May-1991
https://doi.org/10.1007/BF00925471
Fisher AHighnam PRockoff T(1990)A four-processor building block for SIMD processor arraysIEEE Journal of Solid-State Circuits10.1109/4.5215825:2(369-375)Online publication date: Apr-1990
https://doi.org/10.1109/4.52158
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