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Bias scheduling in heterogeneous multi-core architectures

Published: 13 April 2010 Publication History

Abstract

Heterogeneous architectures that integrate a mix of big and small cores are very attractive because they can achieve high single-threaded performance while enabling high performance thread-level parallelism with lower energy costs. Despite their benefits, they pose significant challenges to the operating system software. Thread scheduling is one of the most critical challenges.
In this paper we propose bias scheduling for heterogeneous systems with cores that have different microarchitectures and performance.We identify key metrics that characterize an application bias, namely the core type that best suits its resource needs. By dynamically monitoring application bias, the operating system is able to match threads to the core type that can maximize system throughput. Bias scheduling takes advantage of this by influencing the existing scheduler to select the core type that bests suits the application when performing load balancing operations.
Bias scheduling can be implemented on top of most existing schedulers since its impact is limited to changes in the load balancing code. In particular, we implemented it over the Linux scheduler on a real system that models microarchitectural differences accurately and found that it can improve system performance significantly, and in proportion to the application bias diversity present in the workload. Unlike previous work, bias scheduling does not require sampling of CPI on all core types or offline profiling. We also expose the limits of dynamic voltage/frequency scaling as an evaluation vehicle for heterogeneous systems.

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Published In

cover image ACM Conferences
EuroSys '10: Proceedings of the 5th European conference on Computer systems
April 2010
388 pages
ISBN:9781605585772
DOI:10.1145/1755913
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 April 2010

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Author Tags

  1. heterogeneous architectures
  2. scheduling

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EuroSys '10
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EuroSys '10: Fifth EuroSys Conference 2010
April 13 - 16, 2010
Paris, France

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Overall Acceptance Rate 241 of 1,308 submissions, 18%

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Cited By

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  • (2024)A Novel Priority Based Scheduler for Asymmetric Multi-core Edge ComputingCurrent Trends in Web Engineering10.1007/978-3-031-50385-6_1(7-18)Online publication date: 4-Jan-2024
  • (2023)Efficient Scheduler Live Update for Linux Kernel with ModularizationProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582054(194-207)Online publication date: 25-Mar-2023
  • (2023)A Neural Network-Based Approach to Dynamic Core Morphing for AMPs2023 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES58672.2023.00013(4-9)Online publication date: 18-Dec-2023
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  • (2023)Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder LakeConcurrency and Computation: Practice and Experience10.1002/cpe.781435:25Online publication date: 6-Jun-2023
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  • (2022)Energy-Efficient Cache-Aware Scheduling on Heterogeneous Multicore SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.309058733:1(206-217)Online publication date: 1-Jan-2022
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  • (2022)Dynamic thread mapping for power-efficient many-core systems under performance constraintsMicroprocessors & Microsystems10.1016/j.micpro.2022.10461493:COnline publication date: 1-Sep-2022
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