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Versatile system-level memory-aware platform description approach for embedded MPSoCs

Published: 13 April 2010 Publication History

Abstract

In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations.
In contrast to previous system modeling approaches this approach tries to model the whole system and especially the memory hierarchy in a structural and semantically accessible way. Previous approaches primarily support generation of simulators or retargetable code selectors and thus concentrate on pure behavioral models or describe only the processor instruction set in a semantically accessible way, A simple, database-like, interface is offered to the optimization developer, which in conjunction with the MACCv2 framework enables rapid development of source-level architecture independent optimizations.

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Cited By

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  • (2013)Automatic extraction of pipeline parallelism for embedded heterogeneous multi-core platformsProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555733(1-10)Online publication date: 29-Sep-2013
  • (2013)Automatic extraction of multi-objective aware parallelism for heterogeneous MPSoCs2013 IEEE 6th International Workshop on Multi-/Many-core Computing Systems (MuCoCoS)10.1109/MuCoCoS.2013.6633599(1-10)Online publication date: Sep-2013
  • (2013)Automatic Extraction of Task-Level Parallelism for Heterogeneous MPSoCsProceedings of the 2013 42nd International Conference on Parallel Processing10.1109/ICPP.2013.113(950-959)Online publication date: 1-Oct-2013
  • Show More Cited By

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Published In

cover image ACM Conferences
LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
April 2010
184 pages
ISBN:9781605589534
DOI:10.1145/1755888
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 45, Issue 4
    LCTES '10
    April 2010
    170 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1755951
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 April 2010

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Author Tags

  1. architecture description
  2. channel
  3. component
  4. configuration
  5. definition
  6. energy models
  7. framework

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LCTES '10

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

View all
  • (2013)Automatic extraction of pipeline parallelism for embedded heterogeneous multi-core platformsProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555733(1-10)Online publication date: 29-Sep-2013
  • (2013)Automatic extraction of multi-objective aware parallelism for heterogeneous MPSoCs2013 IEEE 6th International Workshop on Multi-/Many-core Computing Systems (MuCoCoS)10.1109/MuCoCoS.2013.6633599(1-10)Online publication date: Sep-2013
  • (2013)Automatic Extraction of Task-Level Parallelism for Heterogeneous MPSoCsProceedings of the 2013 42nd International Conference on Parallel Processing10.1109/ICPP.2013.113(950-959)Online publication date: 1-Oct-2013
  • (2013)Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662508(1-10)Online publication date: Sep-2013
  • (2012)Multi-objective aware extraction of task-level parallelism using genetic algorithmsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492808(394-399)Online publication date: 12-Mar-2012
  • (2012)ILP-based Memory-Aware Mapping Optimization for MPSoCsProceedings of the 2012 IEEE 15th International Conference on Computational Science and Engineering10.1109/ICCSE.2012.64(413-420)Online publication date: 5-Dec-2012
  • (2012)MAMOTProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.83(743-750)Online publication date: 5-Sep-2012
  • (2012)Multi-objective aware extraction of task-level parallelism using genetic algorithms2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176503(394-399)Online publication date: Mar-2012
  • (2011)Automatic Extraction of Pipeline Parallelism for Embedded Software Using Linear ProgrammingProceedings of the 2011 IEEE 17th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2011.31(699-706)Online publication date: 7-Dec-2011
  • (2011)Mapping Embedded Applications on MPSoCs: The MNEMEE ApproachVLSI 2010 Annual Symposium10.1007/978-94-007-1488-5_10(165-179)Online publication date: 8-Sep-2011
  • Show More Cited By

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