A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs

Reviewer: Vivek Venugopal

Bodily et al. compare applications prototyped on both field-programmable gate arrays (FPGAs) and graphics processing units (GPUs). The authors describe the design effort and performance parameters, such as pipelining and parallelism, when implementing on both platforms. The first application is an optical flow calculation implemented using two algorithms: tensor based and ridge regression based. The tensor-based algorithm was implemented on a Xilinx XUP V2P board consisting of a Virtex-2 Pro XC2VP30, and it was implemented using an embedded development kit (EDK) that indicates the usage of embedded PowerPC and very-high-speed integrated circuits hardware description language (VHDL). It used 10,288 slices, which resulted in a processing power of 64 frames per second (fps) for 640x480 images and 258 fps for 320x240 images. The GPU implementation was done on a NVIDIA 8800 GTX, and the host machine was an Intel Xeon 1.86 gigahertz (GHz) with 1 gigabyte (GB) of random access memory (RAM). The GPU implementation was highly optimized for block sizes, and it resulted in 238 fps for 640x480 images and 847 fps for 320x240 images. The FPGA provided better estimates for power consumption, memory architecture, and flexibility than the GPU. The ridge regression algorithm was implemented on a custom FPGA platform consisting of a Xilinx Virtex-4 FX60 FPGA with two PowerPC embedded processors. The FPGA implementation processed 640x480 images at 15 fps. The GPU implementation was able to process 640x480 images at 158 fps. Both algorithms had better accuracy on the GPU, but the GPU used a single precision floating-point implementation whereas the FPGA used a fixed-point implementation. The development time was longer on the FPGA, resulting in ten to 12 times the design effort as compared to the GPU. The second application is based on the performance evaluation of blocks in communication systems, including the Viterbi decoder, the timing and channel estimator, and the pilot detector. The FPGA implementation of the Viterbi decoder met the timing requirement of 320 microseconds per frame, using 8,790 slices on a Xilinx Virtex-2 Pro. The GPU implementation of the Viterbi decoder provided better throughput over the FPGA by 20 percent, with an increase in latency of 32 times. The estimator used 7,000 slices on a Xilinx Virtex-2 Pro and calculated 70 surface points within the 320 microseconds time frame. The GPU implementation met the 320-microsecond time frame using a combination of coarse and fine search algorithms over the sample sizes. The pilot detector was implemented using seven 1,024-point complex fast Fourier transforms (FFTs), using 16,000 slices on the Xilinx Virtex-2 Pro FPGA. Each FFT on the FPGA took 12 microseconds and used additional logic blocks to keep up with the 41.6M sample data rate. The GPU implementation used the CUFFT library for the FFT processing and took about 60 microseconds for a single 1,024-point FFT. In summary, FPGAs offer more flexibility for custom input/output (I/O) computation, whereas GPUs offer better compute-to-I/O ratio. The memory bottleneck is present for both, as data needs to be sent to both the FPGA and the GPU onboard memory. By leveraging the pipelining of FPGAs and the parallelism of GPUs, readers can use a combination of these architectures to solve real-time applications. Online Computing Reviews Service