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View all- Wang XShi FZhang H(2020)A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip MemoryParallel Architectures, Algorithms and Programming10.1007/978-981-15-2767-8_4(35-47)Online publication date: 26-Jan-2020
Graphics processing units (GPUs) show very high performance when executing many parallel programs; however their use in solving linear recurrence equations is considered difficult because of the sequential nature of the problem. Previously developed ...
Unlike usual VLSI approaches necessary for the computation of intensive Low-Density Parity-Check (LDPC) code decoders, this paper presents flexible software-based LDPC decoders. Algorithms and data structures suitable for parallel computing are proposed ...
The Massively Parallel Processing Project started in 1992 as a priority area of research for the Ministry of Education in Japan. The objective of this research project is to establish the basic technology of massively parallel processing which is ...
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