research-article

Pad assignment for die-stacking System-in-Package design

Authors:

Yu-Chen Lin,

Wai-Kei Mak,

Chris Chu,

Ting-Chi WangAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 249 - 255

https://doi.org/10.1145/1687399.1687445

Published: 02 November 2009 Publication History

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Abstract

Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so as to facilitate wire bonding, is an important physical design problem for SiP design because the quality of a pad assignment solution affects both the cost and performance of a SiP design. In this paper, we study a pad assignment problem, which prohibits the generation of illegal crossings and aims to minimize the total signal wirelength, for die-stacking SiP design. We first consider a variety of special cases and present a minimum-cost maximum-flow based approach to optimally solve them in polynomial time. We then describe an approach, which uses a modified left edge algorithm and an integer linear programming technique, to solve the general case. Encouraging experimental results are shown to support our approaches.

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Cited By

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Mak WLin YChu CWang T(2012)Pad Assignment for Die-Stacking System-in-Package DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.220239531:11(1711-1722)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2202395
Yan JKao CHuang MChen Z(2012)Efficient assignment of inter-die signals for die-stacking SiP design2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6272019(3254-3257)Online publication date: May-2012
https://doi.org/10.1109/ISCAS.2012.6272019
Liu DMak WWang TBahar RLombardi FAtienza DBrunvand E(2010)Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package designProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785580(423-428)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785580

Index Terms

Pad assignment for die-stacking System-in-Package design
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Information

Published In

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

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Research-article

Funding Sources

National Science Council Taiwan

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ICCAD '09

Sponsor:

SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Mak WLin YChu CWang T(2012)Pad Assignment for Die-Stacking System-in-Package DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.220239531:11(1711-1722)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2202395
Yan JKao CHuang MChen Z(2012)Efficient assignment of inter-die signals for die-stacking SiP design2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6272019(3254-3257)Online publication date: May-2012
https://doi.org/10.1109/ISCAS.2012.6272019
Liu DMak WWang TBahar RLombardi FAtienza DBrunvand E(2010)Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package designProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785580(423-428)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785580

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Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design

Pad Assignment for Die-Stacking System-in-Package Design

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