Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems
Pages 77 - 82
Abstract
In this paper, we describe a scalable interconnection network architecture intended for very large multicore processors implemented on stacked chip 3D integrated circuits (3D-IC). These networks provide fully interconnected, low latency, single hop performance with wiring complexity that scales linearly with the size of the network. The enabling technology for these networks is a novel, fully distributed arbitration and control algorithm that operates solely at the edges of the network without the need for any routers within the network core. This paper is focused on a description of that algorithm. We present simulation results for average, worst-case, and per-node latencies showing that our arbitration algorithm performs efficiently, scales for a wide range of partition sizes, and effectively manages highly non-uniform traffic patterns.
References
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Balfour, J., Dally, W. J., "Design tradeoffs for tiled CMP on-chip networks," Proceedings of the 20th Annual international Conference on Super computing, 2006, pp 187--198.
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Siegel, H. J., Interconnection Networks for Large-scale Parallel Processing: Theory and Case Studies, McGraw-Hill, 1990.
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Chiarulli, D. M., Levitan, S. P., Melhem, R. G., et al, "Optoelectronic Buses for High-Performance Computing", IEEE Proceedings, Vol. 82, No. 11, Nov. 1994, pp. 1701--1710.
[4]
Chiarulli, D. M., Levitan, S. P., Melhem, R. G., Teza, J. P., Gravenstreter, G., "Partitioned Optical Passive Star (POPS) Multiprocessor Interconnection Networks with Distributed Control", IEEE Journal of Lightwave Technology, Vol. 14, No. 7, pp. 1601--1612, July 1996.
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Davis, W. R., Wilson, J., Mick, S., et al, "Demystifying 3D ICs: The Pros and Cons of Going Vertical", IEEE Design&Test, v. 22 n. 6, p. 498--510, November 2005.
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http://www.tezzaron.com
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Bailey, David H., "Misleading Performance Reporting in the Supercomputing Field," RNR Technical Report RNR-92-005, December 1, 1992. also in Scientific Programming, vol. 1., no. 2 (Winter 1992), pg. 141--151.
Index Terms
- Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems
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December 2009
98 pages
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Published: 12 December 2009
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Micro-42
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Micro-42: The 42nd Annual IEEE/ACM International Symposium on Microarchitecture
December 12, 2009
New York, New York
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