Cited By
View all- Ho SYuen SPoon HChau TAi YLeong PChoy OPun K(2010)Structured ASIC: Methodology and comparison2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681422(377-380)Online publication date: Dec-2010
Buffer design and optimization for lut-based structured ASIC design styles
Pages 377 - 380
Abstract
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based structured ASIC design style. We design the layouts of two dedicated buffers and extract the technology dependent parameters for evaluations. After that, we propose a channel migration technique, which employs both intra-channel migration and inter-channel migration, to alleviate the sub-channel saturation problem. The experimental results demonstrate that dedicated buffers are essential for structured ASIC design style.
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Index Terms
- Buffer design and optimization for lut-based structured ASIC design styles
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Published In
May 2009
558 pages
ISBN:9781605585222
DOI:10.1145/1531542
- Co-chair:
- Fabrizio Lombardi,
- General Chairs:
- Sanjukta Bhanja,
- Yehia Massoud,
- Program Chair:
- R. Iris Bahar
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Published: 10 May 2009
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View all- Ho SYuen SPoon HChau TAi YLeong PChoy OPun K(2010)Structured ASIC: Methodology and comparison2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681422(377-380)Online publication date: Dec-2010
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