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research-article

Version management alternatives for hardware transactional memory

Authors:

Grigorios Magklis,

Antonio GonzálezAuthors Info & Claims

MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture

Pages 69 - 76

https://doi.org/10.1145/1509084.1509094

Published: 26 October 2008 Publication History

Abstract

Transactional Memory is a promising parallel programming model that addresses the programmability issues of lock-based applications using mechanisms that are transparent to developers. Hardware Transactional Memory (HTM) implements these mechanisms in silicon to obtain better results than fine-grain locking solutions. One of these mechanisms is data version management, that decides how and where the modifications introduced by transactions are stored to guarantee their atomicity and durability.

In this paper, we show that aborts are frequent especially for applications with coarse-grain transactions and many threads, and that this severely restricts the scalability of log-based HTMs. To address this issue, we propose the use of a gated store buffer to accelerate eager version management for log-based HTM. Moreover, we propose a novel design, where the store buffer is used to perform lazy version management (similar to Rock [12]) but overflowed transactions execute with a fallback log-based HTM that uses eager version management.

Assuming an infinite store buffer, we show that lazy version management is better suited to applications with fine-grain transactions while eager version management is better suited to applications with coarse-grain transactions. Limiting the buffer size to 32 entries, we obtain 20.1% average improvement over log-based HTM for applications with fine-grain transactions (using lazy version management) and 54.7% for applications with coarse-grain transactions (using eager version management).

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Cited By

Kim SChoi DRo WGaudiot J(2014)Complexity-Effective Contention Management with Dynamic Backoff for Transactional Memory SystemsIEEE Transactions on Computers10.1109/TC.2013.4963:7(1696-1708)Online publication date: Jul-2014
https://doi.org/10.1109/TC.2013.49
Li GAn HLi QDeng BDai W(2014)Efficient execution of speculative threads and transactions with hardware transactional memoryFuture Generation Computer Systems10.1016/j.future.2013.06.01730:C(242-253)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1016/j.future.2013.06.017
Yan ZJiang HTan YFeng D(2013)An integrated pseudo-associativity and relaxed-order approach to hardware transactional memoryACM Transactions on Architecture and Code Optimization (TACO)10.1145/2400682.24007019:4(1-26)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400701
Show More Cited By

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Version management alternatives for hardware transactional memory

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Published In

cover image ACM Other conferences

MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture

October 2008

88 pages

ISBN:9781605582436

DOI:10.1145/1509084

Conference Chairs:
Pierfrancesco Foglia
Università di Pisa
,
Cosimo Antonio Prete
Università di Pisa
,
Sandro Bartolini
Università di Siena
,
Roberto Giorgi
Università di Siena

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 October 2008

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MEDEA '08

MEDEA '08: The 2008 workshop on MEmory performance: DEaling with Applications, systems and architectures

October 26, 2008

Toronto, Canada

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Overall Acceptance Rate 6 of 9 submissions, 67%

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Cited By

Kim SChoi DRo WGaudiot J(2014)Complexity-Effective Contention Management with Dynamic Backoff for Transactional Memory SystemsIEEE Transactions on Computers10.1109/TC.2013.4963:7(1696-1708)Online publication date: Jul-2014
https://doi.org/10.1109/TC.2013.49
Li GAn HLi QDeng BDai W(2014)Efficient execution of speculative threads and transactions with hardware transactional memoryFuture Generation Computer Systems10.1016/j.future.2013.06.01730:C(242-253)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1016/j.future.2013.06.017
Yan ZJiang HTan YFeng D(2013)An integrated pseudo-associativity and relaxed-order approach to hardware transactional memoryACM Transactions on Architecture and Code Optimization (TACO)10.1145/2400682.24007019:4(1-26)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400701
Huang SJou JHsieh CLin D(2013)Design of a Dynamic Parallel Execution Architecture for Multi-core SystemsAdvances in Intelligent Systems and Applications - Volume 210.1007/978-3-642-35473-1_72(731-740)Online publication date: 2013
https://doi.org/10.1007/978-3-642-35473-1_72
Yan ZJiang HFeng DTian LTan Y(2012)SUVProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium10.1109/IPDPS.2012.22(131-143)Online publication date: 21-May-2012
https://dl.acm.org/doi/10.1109/IPDPS.2012.22
Zhao LChoi WDraper J(2012)SEL-TMProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium10.1109/IPDPS.2012.19(95-106)Online publication date: 21-May-2012
https://dl.acm.org/doi/10.1109/IPDPS.2012.19
Li GAn HLi QDeng BDai W(2012)SeTMProceedings of the 2012 IEEE 18th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2012.77(522-531)Online publication date: 17-Dec-2012
https://dl.acm.org/doi/10.1109/ICPADS.2012.77
Harris TLarus JRajwar R(2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
https://doi.org/10.2200/S00272ED1V01Y201006CAC011
Lupon MMagklis GGonzalez A(2009)FASTMProceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2009.19(293-302)Online publication date: 12-Sep-2009
https://dl.acm.org/doi/10.1109/PACT.2009.19

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