Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining

Fault-tolerant clocking schemes become inevitable when it comes to highly-reliable chip designs. Because of the additional hardware overhead, existing solutions are considerably slower than their non-reliable counterparts. In this paper, we demonstrate ...

We present the first self-stabilizing Byzantine clock synchronization algorithm that has linear convergence time.

With the escalation of clock frequencies and the increasing ratio of wire-to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed very large scale integration (VLSI) chips. Also, with an increasing number of stages ...