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A polynomial-time heuristic approach to approximate a solution to the false path problem

Authors:

Shiang-Tang Huang,

Tai Ming Parng,

Jyuo Min ShyuAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 118 - 122

https://doi.org/10.1145/157485.164622

Published: 01 July 1993 Publication History

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References

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Cited By

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Zhou SYao BChen HZhu YHutton MCollins TSrinivasan SChou NSuaris PCheng C(2007)Efficient Timing Analysis With Known False Paths Using Biclique CoveringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88573726:5(959-969)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.885737
Sait SZahra M(2002)Tabu search based circuit optimizationEngineering Applications of Artificial Intelligence10.1016/S0952-1976(02)00054-415:3-4(357-368)Online publication date: Jun-2002
https://doi.org/10.1016/S0952-1976(02)00054-4
Jing Zeng Abadir MBhadra JAbraham J(2000)Full chip false timing-path identification2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)10.1109/SIPS.2000.886768(703-711)Online publication date: 2000
https://doi.org/10.1109/SIPS.2000.886768
Show More Cited By

Index Terms

A polynomial-time heuristic approach to approximate a solution to the false path problem
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits
    1. Logic circuits
2. Theory of computation
  1. Computational complexity and cryptography
    1. Problems, reductions and completeness

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Zhou SYao BChen HZhu YHutton MCollins TSrinivasan SChou NSuaris PCheng C(2007)Efficient Timing Analysis With Known False Paths Using Biclique CoveringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88573726:5(959-969)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.885737
Sait SZahra M(2002)Tabu search based circuit optimizationEngineering Applications of Artificial Intelligence10.1016/S0952-1976(02)00054-415:3-4(357-368)Online publication date: Jun-2002
https://doi.org/10.1016/S0952-1976(02)00054-4
Jing Zeng Abadir MBhadra JAbraham J(2000)Full chip false timing-path identification2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)10.1109/SIPS.2000.886768(703-711)Online publication date: 2000
https://doi.org/10.1109/SIPS.2000.886768
Sait SYoussef HZahra M(1998)Tabu search based circuit optimizationProceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)10.1109/GLSV.1998.665299(338-343)Online publication date: 1998
https://doi.org/10.1109/GLSV.1998.665299
Kukimoto YGosti WSaldanha ABrayton ROtten RYasuura H(1997)Approximate timing analysis of combinational circuits under the XBD0 modelProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266458(176-181)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266458
Yalcin HHayes JSakallah KRutenbar ROtten R(1997)An approximate timing analysis method for datapath circuitsProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244541(114-118)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.5555/244522.244541
Kukimoto Gosti Saldanha Brayton (1997)Approximate timing analysis of combinational circuits under the XBDO modelProceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-9710.1109/ICCAD.1997.643404(176-181)Online publication date: 1997
https://doi.org/10.1109/ICCAD.1997.643404
Yalcin HHayes JSakallah K(1996)An approximate timing analysis method for datapath circuitsProceedings of International Conference on Computer Aided Design10.1109/ICCAD.1996.569410(114-118)Online publication date: 1996
https://doi.org/10.1109/ICCAD.1996.569410
Wessels DMuzio J(1996)The dangers of simplistic delay modelsJournal of Electronic Testing: Theory and Applications10.1007/BF001360768:1(61-69)Online publication date: 1-Feb-1996
https://dl.acm.org/doi/10.1007/BF00136076
Belkhale KSuess ARudell R(1995)Timing analysis with known false sub graphsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225157(736-740)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225157
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