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Access map pattern matching for data cache prefetch

Authors:

Yasuo Ishii,

Mary Inaba,

Kei HirakiAuthors Info & Claims

ICS '09: Proceedings of the 23rd international conference on Supercomputing

Pages 499 - 500

https://doi.org/10.1145/1542275.1542349

Published: 08 June 2009 Publication History

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Abstract

A novel data prefetching method -- access map pattern matching (AMPM) -- that uses "memory access map" is proposed. The AMPM prefetching concentrate hardware resources on collecting the access footprint of the frequently accessed area which we called "hot zones". 2-bit state is associated with each cache lines of hot zone. A set of these states is called "memory access map". Prefetch requests are generated from the pattern matching of the memory access map. The pattern matching detects multiple memory access patterns in parallel and generates more prefetch requests than conventional prefetchers. The evaluation result shows that the AMPM prefetcher improves performance by 42.0% in FP benchmarks.

References

[1]

Y. Ishii, M. Inaba, and K. Hiraki. Access map pattern matching prefetch: Optimization friendly method. The first JILP Data Prefetching Championship, 2009.

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[2]

K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith. Ac/dc: An adaptive data cache prefetcher. In Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 135--145, 2004.

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[3]

K. J. Nesbit and J. E. Smith. Data cache prefetching using a global history buffer. In Proceedings of the 10th International Symposium on High Performance Computer Architecture, pages 96--105, 2004.

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Martínez Palau FTorrents MArmejach ACasas M(2024)Exploiting Vector Code Semantics for Efficient Data Cache PrefetchingProceedings of the 38th ACM International Conference on Supercomputing10.1145/3650200.3656635(98-109)Online publication date: 30-May-2024
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Zhang YSobotka NPark SJamilan SKhan TKasikci BPokam GLitz HDevietti JTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)RPG2: Robust Profile-Guided Runtime Prefetch GenerationProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640396(999-1013)Online publication date: 27-Apr-2024
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Access map pattern matching for data cache prefetch
1. Computer systems organization
  1. Architectures

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Information

Published In

ICS '09: Proceedings of the 23rd international conference on Supercomputing

June 2009

544 pages

ISBN:9781605584980

DOI:10.1145/1542275

General Chairs:
Michael Gschwind
IBM TJ Watson Research Center, USA
,
Alex Nicolau
UC Irvine, USA
,
Program Chairs:
Valentina Salapura
IBM TJ Watson Research Center, USA
,
José Moreira
IBM TJ Watson Research Center, USA

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2009

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ICS '09: International Conference on Supercomputing

June 8 - 12, 2009

NY, Yorktown Heights, USA

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Wang LZhang XWang SJiang ZLu TChen MLuo SHuang K(2024)Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory AccessACM Transactions on Architecture and Code Optimization10.1145/366347921:3(1-28)Online publication date: 9-May-2024
https://dl.acm.org/doi/10.1145/3663479
Martínez Palau FTorrents MArmejach ACasas M(2024)Exploiting Vector Code Semantics for Efficient Data Cache PrefetchingProceedings of the 38th ACM International Conference on Supercomputing10.1145/3650200.3656635(98-109)Online publication date: 30-May-2024
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Zhang YSobotka NPark SJamilan SKhan TKasikci BPokam GLitz HDevietti JTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)RPG2: Robust Profile-Guided Runtime Prefetch GenerationProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640396(999-1013)Online publication date: 27-Apr-2024
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Cited By

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Data access history cache and associated data prefetching mechanisms

Reducing Cache Pollution via Dynamic Data Prefetch Filtering

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

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