research-article

A novel scheme to reduce short-circuit power in mesh-based clock architectures

Authors:

Gustavo Wilke,

Renan Fonseca,

Cecilia Mezzomo,

Ricardo ReisAuthors Info & Claims

SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design

Pages 117 - 122

https://doi.org/10.1145/1404371.1404409

Published: 01 September 2008 Publication History

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Abstract

Meshes are widely used for distributing clock in high performance designs. In the past, they were used exclusively for microprocessors, now they are being integrated into the ASIC design flow as well. A mesh has a much smaller skew and jitter, but the high power consumption limits its applicability. In this work, we address the high power consumption of mesh architectures. We propose a novel design for mesh buffers to minimize the short circuit current caused by the different arrival times of the clock signal at mesh buffer inputs. By reducing the short circuit current, we show that the mesh power consumption is reduced by up to 59% and skew by 22%.

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Cited By

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Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Guthaus MWilke G(2014)Variability-Aware Clock DesignCircuit Design for Reliability10.1007/978-1-4614-4078-9_12(255-272)Online publication date: 16-Oct-2014
https://doi.org/10.1007/978-1-4614-4078-9_12
Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442102
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Index Terms

A novel scheme to reduce short-circuit power in mesh-based clock architectures
1. Hardware

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Information & Contributors

Information

Published In

SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design

September 2008

256 pages

ISBN:9781605582313

DOI:10.1145/1404371

General Chair:
Marcelo Lubaszewski
UFRGS, Brazil
,
Program Chairs:
Michel Renovell
LIRMM, France
,
Rajesh Gupta
UCSD, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2008

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SBCCI08

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SBCCI08: 21st Symposium on Integrated Circuits and System Design

September 1 - 4, 2008

Gramado, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

View all

Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Guthaus MWilke G(2014)Variability-Aware Clock DesignCircuit Design for Reliability10.1007/978-1-4614-4078-9_12(255-272)Online publication date: 16-Oct-2014
https://doi.org/10.1007/978-1-4614-4078-9_12
Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442102
Shim SMo MKim SShin Y(2013)Analysis and minimization of short-circuit current in mesh clock network2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657082(459-462)Online publication date: Oct-2013
https://doi.org/10.1109/ICCD.2013.6657082
Hu XGuthaus M(2012)Distributed LC Resonant Clock Grid SynthesisIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2012.219067159:11(2749-2760)Online publication date: Nov-2012
https://doi.org/10.1109/TCSI.2012.2190671

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