GMDS: hardware implementation of novel real output queuing architecture
Authors: 
R. Arteaga, F. Tobajas, R. Esper-Chain, V. de Armas, Roberto SarmientoAuthors Info & Claims
Pages 1450 - 1455
Abstract
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (Gigabit MultiDrop Switch) and its main features are the switch matrix replacement by the multidrop backplane -increasing system reliability-, variable lenght packet switching support -avoiding bandwidth efficient loss-, multiple output queuing structure for supporting QoS (Quality of Service) and a minimum speedup.
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Esper-Chain, R., Tobajas, F., Tubio, O., Arteaga, R., de Armas, V. and Sarmiento, R. A gigabit multidrop serial link for high-speed digital systems based on assymetrical power splitters. IEEE Transactions on Circuits and Systems II: Express Briefs, 52(1):5--9, January 2005.
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Index Terms
- GMDS: hardware implementation of novel real output queuing architecture
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Published: 10 March 2008
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