More Web Proxy on the site http://driver.im/

article

Free access

Instruction-level parallelism in Prolog: analysis and architectural support

Authors:

Alessandro De Gloria,

Paolo FaraboschiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 20, Issue 2

Pages 224 - 233

https://doi.org/10.1145/146628.139730

Published: 01 April 1992 Publication History

Abstract

The demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of prolog. Unlike past microcoded implementation based on the Warren machine model, novel trends in high performance Prolog processors suggest the implementation of RISC-based processors committed to prolog only through the adoption of a few basic dedicated features, like the Berkeley Abstract Machine (BAM) processor.

Following the idea of using a smart compiler for a simple instruction set, the SYMBOL project represents an experiment in applying global compaction techniques and VLIW design philosophy to the static exploitation of instruction-level parallelism in Prolog.

This paper presents code analysis results and shows how we can approach the theoretical speed-up limit (about 3) imposed by Amdahl's law on shared memory models, by means of global code optimizations and a suitable architectural support. In addition, we show implementation details and some preliminary data of a VLSI prototype architecture.

References

[1]

G. M. Amdahl, "Validity of the single processor approach to achieving large scale computing capabilities", Proc. AFIPS 1967 Spring Joint Computer Conference, N.J., 1967.

Digital Library

[2]

A. Aho, R. Seth J, D. Ullman, Compilers: Principles, Techm'ques and Tools, Addison Wesley, 1986.

Digital Library

[3]

H. Benker, L Beacco, S. Bescos et al., " KCM: A Knowledge Crunching Machine", 16th International Symposium on Computer Architecture (ISCA16), pp. 186-194, 1989.

Digital Library

[4]

G. Borriello, A. Cherenson, P. Danzig, M. Nelson, "Special or General-PtnImse Hardware for Prolog: A Comparison", Technical report, University of California at Berkeley, 1986.

Digital Library

[5]

T. Dobry, A High Performance Architecture for Prolog, PhD Thesis, University of California at Berkeley, 1987.

Digital Library

[6]

W.F.Clocksin, C.S. Mellish, Programming in Prolog, Springer-Verlag, New York, 1981.

Digital Library

[7]

J. Ellis, Bulldog: A Compiler for VL{W architectures, The MIT Press, Boston, Mass., 1985.

Digital Library

[8]

A.De Gloria, P.Faraboschi, "An Evaluation System for Application Specific Architectures", 23rd International Workshop on Microprogramming and Microarchitecture (MICRO23), 1990.

Digital Library

[9]

A.De Gloria, P.Faraboschi, E. Guidetti, "A Archi~ for Prolog", IEEE MicroArch, Vol. 6, N. 1, Nov 1991, pp 27-32.

Digital Library

[10]

J. Fisher, "Trace Scheduling: a technique for global microcxxte compaction", IEEE Trans. on Computer, vol. C-30, pp. 478-490, 1981.

[11]

J. Fisher, "Very Long Instruction Word Architectures and the ELI-512", Proc. of l Oth International Symposium on Computer Architecture (ISCAIO), 1983.

Digital Library

[12]

R. Haygood, A Prolog Benchmark Suite for Aquarius, Report. No. UCB/UCSD 89/509, University of California at Berkeley, Apr. 1989.

Digital Library

[13]

J. Hennessy, "VLSI Processor Architecture", IEEE Trans. on Computer, pp. 1221-1246, 1983.

[14]

J. Hennessy, D. Patterson. Computer Architecture: a Quantitative Approach, Morgan Kaufmann Publ., San Mateo, CA, 1990.

Digital Library

[15]

B. Holmer, B. Sano, M. Carlton, P. Van Roy, R. Haygood, W. Bush, A. Despain, J. Pendleton, T. Dobry,"Fast Prolog with an Extended General Purlx)se Architecture", 17the International Symposium on Computer Architecture (ISCA17), pp. 282-291, 1990.

Digital Library

[16]

M. Katevenis, Reduced Instruction Set computer for VLSI, Computer Science Division (EECS) UCB/CSB 83/141, University of California At Berkeley, Oct. 1983.

Digital Library

[17]

, R. Kowalski, Logic for Problem Solving, Elsevier Publ., North-Holland, 1979.

Digital Library

[18]

E. Tick, Studies in Prolog Architectures, Technical Report, Stanford University, 1987.

[19]

P. Van Roy, A Prolog Compiler for the PLM, Master Thesis, University of California at Berkeley, 1984

[20]

P. Van Roy, Can Logic Programming Execute as Fast as Imperative Progr~8?, PhD Th~sis, R~port No. UCB/CSD 901600 (EECS) University of California at Berkeley, CA, Dec. 1990.

Digital Library

[21]

D. Warren, An Abstract Prolog Instruction Set, Artificial Intelligence Center, SRI International, 1983.

[22]

M. Wolfe, Optimizing supercompilers for supercomputcrs, The MIT Press, Boston, Mass. 1989.

Digital Library

Cited By

Bellotti FBricco EBruzzone ACaviglia DDi Zitti EGastaldo PGrosso DMagnani LOlivieri MRaggio MValle MVerri ABerta R(2024)Alessandro De Gloria, a Pioneer in Electronic Engineering ApplicationsApplications in Electronics Pervading Industry, Environment and Society10.1007/978-3-031-48121-5_1(3-11)Online publication date: 13-Jan-2024
https://doi.org/10.1007/978-3-031-48121-5_1
Kim HGaudiot J(1994)Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel ArchitecturesProceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques10.5555/647042.713814(225-234)Online publication date: 24-Aug-1994
https://dl.acm.org/doi/10.5555/647042.713814
Ruey-Liang Ma Chung-Ping Chung (1994)Branch prediction for enhancing fine-grained parallelism in PrologProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590462(744-751)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590462
Show More Cited By

Index Terms

Instruction-level parallelism in Prolog: analysis and architectural support

Recommendations

Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a ...
Enhancing instruction level parallelism through compiler-controlled speculation
Instruction-level parallelism in Prolog: analysis and architectural support
ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

The demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of prolog. Unlike past microcoded implementation based on the Warren machine model, novel trends in high ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 20, Issue 2

Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

May 1992

429 pages

ISSN:0163-5964

DOI:10.1145/146628

Editor:
Allan Gotlieb
New York Univ., New York, NY

Issue’s Table of Contents

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture
May 1992
439 pages
ISBN:0897915097
DOI:10.1145/139669
Chairman:
Allan Gottlieb
New York Unvi., New York, NY

Copyright © 1992 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

Published in SIGARCH Volume 20, Issue 2

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
372
Total Downloads

Downloads (Last 12 months)65
Downloads (Last 6 weeks)9

Reflects downloads up to 04 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Bellotti FBricco EBruzzone ACaviglia DDi Zitti EGastaldo PGrosso DMagnani LOlivieri MRaggio MValle MVerri ABerta R(2024)Alessandro De Gloria, a Pioneer in Electronic Engineering ApplicationsApplications in Electronics Pervading Industry, Environment and Society10.1007/978-3-031-48121-5_1(3-11)Online publication date: 13-Jan-2024
https://doi.org/10.1007/978-3-031-48121-5_1
Kim HGaudiot J(1994)Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel ArchitecturesProceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques10.5555/647042.713814(225-234)Online publication date: 24-Aug-1994
https://dl.acm.org/doi/10.5555/647042.713814
Ruey-Liang Ma Chung-Ping Chung (1994)Branch prediction for enhancing fine-grained parallelism in PrologProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590462(744-751)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590462
Costa ADe Gloria AFaraboschi POlivieri MWolfe AMangione-Smith W(1993)An analysis of dynamic scheduling techniques for symbolic applicationsProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255284(185-191)Online publication date: 1-Dec-1993
https://dl.acm.org/doi/10.5555/255235.255284
Rau B(1993)Dynamically scheduled VLIW processorsProceedings of the 26th Annual International Symposium on Microarchitecture10.1109/MICRO.1993.282744(80-92)Online publication date: 1993
https://doi.org/10.1109/MICRO.1993.282744
Baldi LCivera PIurlaro AMasera GPagni APiccinini GPoluzzi RRoch MZamboni M(1993)PROXIMA: PROlog eXecutIon MAchineIEEE Journal of Solid-State Circuits10.1109/4.21000428:3(362-370)Online publication date: Mar-1993
https://doi.org/10.1109/4.210004
De Gloria AFaraboschi POlivieri MGuidetti E(1992)ASIC and board design of a high performance parallel architectureProceedings Euro ASIC '9210.1109/EUASIC.1992.228047(244-249)Online publication date: 1992
https://doi.org/10.1109/EUASIC.1992.228047

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents