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An adaptive resource partitioning algorithm for SMT processors

Authors:

C. Mani KrishnaAuthors Info & Claims

PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques

Pages 230 - 239

https://doi.org/10.1145/1454115.1454148

Published: 25 October 2008 Publication History

Abstract

Simultaneous Multithreading (SMT) increases processor throughput by allowing the parallel execution of several threads. However, fully sharing processor resources may cause resource monopolization by a single thread or other misallocations, resulting in overall performance degradation. Static resource partitioning techniques have been suggested, but are not as effective as dynamically controlling the resource usage of each thread since program behavior does change during its execution.

In this paper, we propose an Adaptive Resource Partitioning Algorithm (ARPA) that dynamically assigns resources to threads according to thread behavior changes. ARPA analyzes the resource usage efficiency of each thread in a time period and assigns more resources to threads which can use them in a more efficient way. The purpose of ARPA is to improve the efficiency of resource utilization, thereby improving overall instruction throughput. Our simulation results on a set of 42 multiprogramming workloads show that ARPA outperforms the traditional fetch policy ICOUNT by 55.8% with regard to overall instruction throughput and achieves a 33.8% improvement over Static Partitioning. It also outperforms the current best dynamic resource allocation technique, Hill-climbing, by 5.7%. Considering fairness accorded to each thread, ARPA attains 43.6%, 18.5% and 9.2% improvements over ICOUNT, Static Partitioning and Hill-climbing, respectively, using a common fairness metric.

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Cited By

Stojkovic JChoukse ESaurez EGoiri ÍTorrellas J(2024)Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00103(1397-1412)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00103
Sari SDemir OKucuk G(2024)Exploring Machine Learning Approaches for QoS Prediction on SMT Processors2024 11th International Conference on Future Internet of Things and Cloud (FiCloud)10.1109/FiCloud62933.2024.00054(302-307)Online publication date: 19-Aug-2024
https://doi.org/10.1109/FiCloud62933.2024.00054
Gerogiannis GTorrellas J(2023)Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-MakingProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623780(698-713)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623780
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Index Terms

An adaptive resource partitioning algorithm for SMT processors
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing

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Published In

cover image ACM Conferences

PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques

October 2008

328 pages

ISBN:9781605582825

DOI:10.1145/1454115

General Chair:
Andreas Moshovos
University of Toronto, Canada
,
Program Chairs:
David Tarditi
Microsoft, USA
,
Kunle Olukotun
Stanford University, USA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 25 October 2008

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PACT '08

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PACT '08: International Conference on Parallel Architectures and Compilation Techniques

October 25 - 29, 2008

Ontario, Toronto, Canada

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

Stojkovic JChoukse ESaurez EGoiri ÍTorrellas J(2024)Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00103(1397-1412)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00103
Sari SDemir OKucuk G(2024)Exploring Machine Learning Approaches for QoS Prediction on SMT Processors2024 11th International Conference on Future Internet of Things and Cloud (FiCloud)10.1109/FiCloud62933.2024.00054(302-307)Online publication date: 19-Aug-2024
https://doi.org/10.1109/FiCloud62933.2024.00054
Gerogiannis GTorrellas J(2023)Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-MakingProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623780(698-713)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623780
Gemirter CKucuk G(2021)Fine-Tuning Throughput and QoS on SMT Cores2021 6th International Conference on Computer Science and Engineering (UBMK)10.1109/UBMK52708.2021.9559021(581-586)Online publication date: 15-Sep-2021
https://doi.org/10.1109/UBMK52708.2021.9559021
Margaritov AGupta SGonzalez-Alberquilla RGrot B(2019)Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00024(15-27)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00024
Inal GKucuk G(2018)Application of Machine Learning Techniques on Prediction of Future Processor Performance2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW.2018.00044(190-195)Online publication date: Nov-2018
https://doi.org/10.1109/CANDARW.2018.00044
Güngörer HKüçük G(2018)Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for PerformanceComputer and Information Sciences10.1007/978-3-030-00840-6_5(41-48)Online publication date: 16-Sep-2018
https://doi.org/10.1007/978-3-030-00840-6_5
Zhang YLin W(2016)Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processorsMicroprocessors & Microsystems10.1016/j.micpro.2016.06.00245:PB(270-282)Online publication date: 1-Sep-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.06.002
Porter LLaurenzano MTiwari AJundt AWard, Jr. WCampbell RCarrington L(2015)Making the Most of SMT in HPCACM Transactions on Architecture and Code Optimization10.1145/268765111:4(1-26)Online publication date: 9-Jan-2015
https://dl.acm.org/doi/10.1145/2687651
Sahba ASahba RWei-Ming Lin (2014)Improving IPC in simultaneous multi-threading (SMT) processors by capping IQ utilization according to dispatched memory instructions2014 World Automation Congress (WAC)10.1109/WAC.2014.6936190(893-899)Online publication date: Aug-2014
https://doi.org/10.1109/WAC.2014.6936190
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