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Foundations of the C++ concurrency memory model

Authors:

Sarita V. AdveAuthors Info & Claims

PLDI '08: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation

Pages 68 - 78

https://doi.org/10.1145/1375581.1375591

Published: 07 June 2008 Publication History

Abstract

Currently multi-threaded C or C++ programs combine a single-threaded programming language with a separate threads library. This is not entirely sound [7].

We describe an effort, currently nearing completion, to address these issues by explicitly providing semantics for threads in the next revision of the C++ standard. Our approach is similar to that recently followed by Java [25], in that, at least for a well-defined and interesting subset of the language, we give sequentially consistent semantics to programs that do not contain data races. Nonetheless, a number of our decisions are often surprising even to those familiar with the Java effort:

We (mostly) insist on sequential consistency for race-free programs, in spite of implementation issues that came to light after the Java work.

We give no semantics to programs with data races. There are no benign C++ data races.

We use weaker semantics for trylock than existing languages or libraries, allowing us to promise sequential consistency with an intuitive race definition, even for programs with trylock.

This paper describes the simple model we would like to be able to provide for C++ threads programmers, and explain how this, together with some practical, but often under-appreciated implementation constraints, drives us towards the above decisions.

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Cited By

Geeson LBrotherston JDijkstra WDonaldson ASmith LSorensen TWickerson J(2024)Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics ImplementationsProceedings of the ACM on Programming Languages10.1145/36897278:OOPSLA2(442-467)Online publication date: 8-Oct-2024
https://dl.acm.org/doi/10.1145/3689727
Hammond ALiu ZPérami TSewell PBirkedal LPichon-Pharabod J(2024)An Axiomatic Basis for Computer Programming on the Relaxed Arm-A Architecture: The AxSL LogicProceedings of the ACM on Programming Languages10.1145/36328638:POPL(604-637)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632863
Zhang YWang MWang WMai YHuang HYu Z(2024)Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00056(671-685)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00056
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Index Terms

Foundations of the C++ concurrency memory model
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Concurrent programming structures

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Published In

cover image ACM Conferences

PLDI '08: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation

June 2008

396 pages

ISBN:9781595938602

DOI:10.1145/1375581

General Chair:
Rajiv Gupta
University of California, Riverside, USA
,
Program Chair:
Saman Amarasinghe
Massachusetts Institute of Technology, USA

ACM SIGPLAN Notices Volume 43, Issue 6
PLDI '08
June 2008
382 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1379022
Issue’s Table of Contents

Copyright © 2008 ACM.

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Published: 07 June 2008

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PLDI '08: ACM SIGPLAN Conference on Programming Language Design and Implementation

June 7 - 13, 2008

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Cited By

Geeson LBrotherston JDijkstra WDonaldson ASmith LSorensen TWickerson J(2024)Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics ImplementationsProceedings of the ACM on Programming Languages10.1145/36897278:OOPSLA2(442-467)Online publication date: 8-Oct-2024
https://dl.acm.org/doi/10.1145/3689727
Hammond ALiu ZPérami TSewell PBirkedal LPichon-Pharabod J(2024)An Axiomatic Basis for Computer Programming on the Relaxed Arm-A Architecture: The AxSL LogicProceedings of the ACM on Programming Languages10.1145/36328638:POPL(604-637)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632863
Zhang YWang MWang WMai YHuang HYu Z(2024)Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00056(671-685)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00056
Geeson LSmith L(2024)Compiler Testing with Relaxed Memory Models2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO57630.2024.10444836(334-348)Online publication date: 2-Mar-2024
https://doi.org/10.1109/CGO57630.2024.10444836
Wrenger LTöllner DLohmann D(2024)Analyzing the memory ordering models of the Apple M1Journal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103102149:COnline publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1016/j.sysarc.2024.103102
Sato SMizuhashi TKimura GTaura K(2024)Efficiently Adapting Stateless Model Checking for C11/C++11 to Mixed-Size AccessesProgramming Languages and Systems10.1007/978-981-97-8943-6_17(346-364)Online publication date: 23-Oct-2024
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Lee SCho MMargalit RHur CLahav O(2023)Putting Weak Memory in Order via a Promising Intermediate RepresentationProceedings of the ACM on Programming Languages10.1145/35912977:PLDI(1872-1895)Online publication date: 6-Jun-2023
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Tunç HAbdulla PChakraborty SKrishna SMathur UPavlogiannis A(2023)Optimal Reads-From Consistency Checking for C11-Style Memory ModelsProceedings of the ACM on Programming Languages10.1145/35912517:PLDI(761-785)Online publication date: 6-Jun-2023
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Gouicem RSprokholt DRuehl JRocha RSpink TChakraborty SBhatotia PAamodt TJerger NSwift M(2023)Risotto: A Dynamic Binary Translator for Weak Memory Model ArchitecturesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3567955.3567962(107-122)Online publication date: 25-Mar-2023
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Shahare VChabbi MHegde NAgrawal KShun J(2023)Protecting Locks Against Unbalanced Unlock()Proceedings of the 35th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3558481.3591091(199-211)Online publication date: 17-Jun-2023
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