Cited By
View all- Yoon KHyun DShin YChen DHomayoun HTaskin B(2018)Fast Timing Analysis of Non-Tree Clock Network with Shorted WiresProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194598(279-284)Online publication date: 30-May-2018
- Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
- Hu XCondley WGuthaus MGroeneveld PSciuto DHassoun S(2012)Library-aware resonant clock synthesis (LARCS)Proceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228389(145-150)Online publication date: 3-Jun-2012
- Show More Cited By