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Information theoretic approach to address delay and reliability in long on-chip interconnects

Published: 05 November 2006 Publication History

Abstract

With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, the effects of crosstalk are detrimental to the overall system performance due to the large delays and un-reliability involved. This paper presents an information theoretic approach to address delay and reliability in long interconnects. A framework to calculate the capacity of a physical wire is laid out herein. The results for 8-bit wide buses of varying lengths in 0.1μm technology are also presented. The wires are modeled based on their calculated parasitic (R, L, C) values and the coupling (C, L) parameters. Using this model, results are obtained for the data transfer capacity of long interconnects. It is seen that for wide buses, the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication-theory, these "good" signals arriving early can be used to predict/correct the "few" signals arriving late. Further, results show that for every bus configuration, there exists an optimal frequency of transmission that will result in the maximum data transfer rate. Also, this optimal frequency is higher than the pessimistic worst case delay based clock design.

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Cited By

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  • (2011)Energy and reliability oriented mapping for regular Networks-on-ChipProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999966(121-128)Online publication date: 1-May-2011
  • (2011)IntroductionTransient and Permanent Error Control for Networks-on-Chip10.1007/978-1-4614-0962-5_1(1-17)Online publication date: 27-Sep-2011
  • (2009)Robust interconnect communication capacity algorithm by geometric programmingProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514938(19-26)Online publication date: 29-Mar-2009

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            cover image ACM Conferences
            ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
            November 2006
            147 pages
            ISBN:1595933891
            DOI:10.1145/1233501
            Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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            Published: 05 November 2006

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            View all
            • (2011)Energy and reliability oriented mapping for regular Networks-on-ChipProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999966(121-128)Online publication date: 1-May-2011
            • (2011)IntroductionTransient and Permanent Error Control for Networks-on-Chip10.1007/978-1-4614-0962-5_1(1-17)Online publication date: 27-Sep-2011
            • (2009)Robust interconnect communication capacity algorithm by geometric programmingProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514938(19-26)Online publication date: 29-Mar-2009

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