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Linearized CMOS active resistor independent on the bulk effect

Published: 11 March 2007 Publication History

Abstract

This paper presents a new linearity improvement technique for a CMOS active resistor. In order to minimize the silicon occupied area, an original method will be designed, having the result of about two order of magnitude reducing area with respect to a classical resistor. The circuit theoretical estimated linearity error is 0.35% for an input range of ±500mV, confirmed by SPICE simulations. The circuit is designed for low-voltage low-power application (a supply voltage of about ±3.3V) and it is implemented in 0.35μm CMOS technology. The layout area (60μm x 80μm) is minimized using an original technique based on an optimal implementation of the current-controlled voltage generators from the active resistor circuit.

References

[1]
Wang, Z. Current-controlled Linear MOS Earthed and Floating Resistors and Application. IEEE Proceedings on Circuits, Devices and Systems (Dec. 1990), 479--481.
[2]
Sellami, L. Linear Bilateral CMOS Resistor for Neural-type Circuits. Proceedings of the 40th Midwest Symposium on Circuits and Systems (Ian. 1997), 1330--1333.
[3]
Singh, S.P., Hansom, J.V., and Vlach, J. A New Floating Resistor for CMOS Technology. IEEE Transactions on Circuits and Systems (Sept. 1989), 1217--1220.
[4]
Sakurai, S., and Ismail, M. A CMOS Square-law Programmable Floating Resistor. IEEE International Symposium on Circuits and Systems (June 1993), 1184--1187.
[5]
Papazoglou, C.A., and Karybakas, C.A. Electronically Tunable Floating CMOS Resistor Independent of the MOS Parameters and Temperature. Proceedings of Electronics, Circuits and Systems, The 6th IEEE International Conference on ICECS (Sept. 1999), 311--314.

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. CMOS design
    2. active resistor
    3. area minimization
    4. linearity

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    GLSVLSI07
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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2020)Implementation of Analog Perceptron as an Essential Element of Configurable Neural NetworksSensors10.3390/s2015422220:15(4222)Online publication date: 29-Jul-2020
    • (2010)Circuit-Level Design of Human Voice SourceInternational Journal of Computer Theory and Engineering10.7763/IJCTE.2010.V2.189(482-490)Online publication date: 2010
    • (2010)MOS Modelling and Simulation of Human GlottisProceedings of the 2010 International Conference on Signal Acquisition and Processing10.1109/ICSAP.2010.59(31-35)Online publication date: 9-Feb-2010
    • (2008)An Electronically Tunable Linear or Nonlinear MOS ResistorIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2008.92006355:9(2573-2583)Online publication date: Oct-2008

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