More Web Proxy on the site http://driver.im/

article

Architectural contesting: exposing and exploiting temperamental behavior

Authors:

Hashem H. Najaf-abadi,

Eric RotenbergAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 3

Pages 28 - 35

https://doi.org/10.1145/1294313.1294321

Published: 01 June 2007 Publication History

Abstract

Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such approaches are prone to a fundamental trade-off between the architectural diversity they can provide and the latency of architectural change, their fixed-configuration performance and the complexity of finding the best architectural configuration for the workload at hand. In this study we argue that the full potential of dynamic architectural customization can only be achieved by diminishing the effect of the degree of available architectural diversity on the aforementioned performance factors.

The performance of a statically designed processing core in a heterogeneous multi-core system is independent of the architectural diversity available. In addition, it is apparent that concurrent execution of code on differently architected cores automatically reveals which architecture is more suitable for the characteristics of a particular workload.

We therefore propose architectural contesting; the redundant execution of code on a number of differently architected processors (each customized for a different set of workload characteristics) in a leader follower arrangement, such that the leader and follower cores continuously shift roles as one core or the other becomes more favorable for new code phases. In this manner effective execution is naturally transferred from one static architecture to the other with little latency.

In this study, we show that the contesting of only processor width can yield an average speedup of 7.5% and up to 12.5% in integer SPEC benchmarks.

References

[1]

S. Palacharla, N. P. Jouppi, and J. E. Smith, "Complexity-effective superscalar processors", In the 24th Inter. Symp. on Comp. Arch. (ISCA), June 2--4, 1997.

Digital Library

[2]

R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. "Single-ISA Heterogeneous Multi-core Architectures: The Potential for Processor Power Reduction", In Inter. Symp. on Micro (MICRO), Dec. 2003

Digital Library

[3]

J. E. Smith. "Instruction-level distributed processing", IEEE Computer, 34(4):59.65, April 2001.

Digital Library

[4]

S. Balakrishnan, R. Rajwar, M. Upton, K. Lai, "The Impact of Performance Asymmetry in Emerging Multicore Architectures" 32nd Inter Symp on Comp Arch., June 2005.

Digital Library

[5]

A. Dhodapkar and J. Smith. "Managing Multi-Configuration Hardware via Dynamic Working Set Analysis", In Inter. Symp. on Comp. Arch. (ISCA), pp 233--244, 2002.

Digital Library

[6]

M. Huang, J. Renau, and J. Torrellas. "Profile-based energy reduction for high-performance processors". In 4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO4), Dec. 2001.

[7]

T. Sherwood, S. Sair, and B. Calder, "Phase tracking and prediction", In 30th Inter. Symp. on Comp. Arch., 2003

Digital Library

[8]

H. Akkary and M. A. Driscoll, "A Dynamic Multithreading Processor", in Proc. 31st. Ann. Int. Symp. on Micro, 1998.

Digital Library

[9]

K. Sundaramoorthy, Z. Purser, and E. Rotenberg. "Slipstream Processors: Improving both Performance and Fault Tolerance" ASPLOS-IX, Nov. 2000.

Digital Library

[10]

D. Albonesi. "Dynamic IPC/clock rate optimization", the 25th Inter. Symp. on Comp. Arch. (ISCA), pp. 282--292, June 1998.

Digital Library

[11]

D. Ponomarev, G. Kucuk, O. Ergin, K. Ghose, P. Kogge, "Energy-Efficient Issue Queue Design", IEEE Transactions on Very Large Scale Integration Systems, 2003.

Digital Library

[12]

D. Folegnani and A. Gonzlez. "Energy-Effective Issue Logic", Inter. Symp. on Comp. Arch. (ISCA) 2001.

Digital Library

[13]

S.-H. Yang, M. D. Powell, B. Falsafi, K. Roy, and T. Vijaykumar, "An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance caches" In Inter. Symp. on High-Perf. Comp. Arch., pp 147--157, 2001.

Digital Library

[14]

R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. "Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures" In Inter. Symp. on Micro., pp 245--257, December 2000.

Digital Library

[15]

D. H. Albonesi et al. "Dynamically Tuning Processor Resources with Adaptive Processing". In IEEE Computer, December 2003.

Digital Library

[16]

R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas, "Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures", Inter. Symp. on Micro., 2000.

Digital Library

[17]

M. Huang, J. Renau, J. Torrellas, "Positional Adaptation of Processors: Application to Energy Reduction", Inter. Symp. on Comp. Arch., 2003.

Digital Library

[18]

E. Hao, P. Chang, and Y. Patt, "The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited", 27^th Inter. Symp. on Micro. (MICRO), pp. 228--232, 1994.

Digital Library

[19]

K. Compton and S. Hauck. "Reconfigurable computing: A survey of systems and software", ACM Computing Surveys, 34(2), 2002.

Digital Library

[20]

S. G. Dropsho, G. Semeraro, D. H. Albonesi, G. Magklis, M. L. Scott, "Dynamically Trading Frequency for Complexity in a GALS Microprocessor", Inter. Symp. on Microarch. (MICRO), pp. 157--168, 2004.

Digital Library

[21]

D. Burger, S. Kaxiras, and J. R. Goodman, "DataScalar Architectures", 24th Inter. Symp. on Comp. Arch. (ISCA), June, 1997.

Digital Library

[22]

L. Chen, D. H. Albonesi, and S. Dropsho, "Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture", IBM Watson Conf. on the Intera. Between Arch., Circuits, and Compilers, pp. 136--143, Oct. 2004.

[23]

R. Kumar, D. M. Tullsen, N. P. Jouppi "Core architecture optimization for heterogeneous chip multiprocessors", Parallel Arch. and Comp. Tech. (PACT), pp. 23--32, 2006.

Digital Library

[24]

M. Cintra, J. F. Martínez, and J. Torrellas. Architectural support for scalable speculative parallelization in shared-memory multiprocessors. In Inter. Symp. on Comp. Arch. (ISCA), pp. 13--24, 2000

Digital Library

[25]

M. Franklin, "Multiscalar Processors", Kluwer Academic Publishers, 2002.

Digital Library

[26]

D. Tarjan, S. Thoziyoor; N. P. Jouppi, "CACTI 4.0", Technical report HPL-2006-86, 2006.

Cited By

Liu JDi ZLiu SPu CWu LPan L(2014)Finding Optimized Deployment Strategy for Multitenant Services by Iterative StagingProceedings of the 2014 Asia-Pacific Services Computing Conference10.1109/APSCC.2014.30(129-135)Online publication date: 4-Dec-2014
https://dl.acm.org/doi/10.1109/APSCC.2014.30

Index Terms

Architectural contesting: exposing and exploiting temperamental behavior

Recommendations

Architectural Considerations for Application-Specific Counterflow Pipelines
ARVLSI '99: Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI

Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application- specific processors are especially promising for embedded systems (e.g., digital cameras, cellular phones, etc.) where a ...
Architectural and compiler mechanisms for accelerating single thread applications on multicore processors
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements

Multimedia SIMD extensions such as MMX and AltiVec speed up media processing; however, our characterization shows that the attributes of current general-purpose processors enhanced with SIMD extensions do not match very well with the access patterns and ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 3

Special issue on the 2006 reconfigurable and adaptive architecture workshop

June 2007

55 pages

ISSN:0163-5964

DOI:10.1145/1294313

Issue’s Table of Contents

Copyright © 2007 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2007

Published in SIGARCH Volume 35, Issue 3

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
238
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Liu JDi ZLiu SPu CWu LPan L(2014)Finding Optimized Deployment Strategy for Multitenant Services by Iterative StagingProceedings of the 2014 Asia-Pacific Services Computing Conference10.1109/APSCC.2014.30(129-135)Online publication date: 4-Dec-2014
https://dl.acm.org/doi/10.1109/APSCC.2014.30

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents