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Secure FPGA circuits using controlled placement and routing

Published: 30 September 2007 Publication History

Abstract

In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied sub-module. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuits can be successfully attacked.

References

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Cited By

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  • (2024)Enabling Secure and Efficient Sharing of Accelerators in Expeditionary SystemsJournal of Hardware and Systems Security10.1007/s41635-024-00148-48:2(94-112)Online publication date: 8-May-2024
  • (2023)MeLPUF: Memory-in-Logic PUF Structures for Low-Overhead IC Authentication2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)10.1109/PAINE58317.2023.10317943(1-7)Online publication date: 24-Oct-2023
  • (2022)Gate-Level Hardware Countermeasure Comparison against Power Analysis AttacksApplied Sciences10.3390/app1205239012:5(2390)Online publication date: 25-Feb-2022
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    cover image ACM Conferences
    CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
    September 2007
    284 pages
    ISBN:9781595938244
    DOI:10.1145/1289816
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 30 September 2007

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    ESWEEK07
    ESWEEK07: Third Embedded Systems Week
    September 30 - October 3, 2007
    Salzburg, Austria

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    Cited By

    View all
    • (2024)Enabling Secure and Efficient Sharing of Accelerators in Expeditionary SystemsJournal of Hardware and Systems Security10.1007/s41635-024-00148-48:2(94-112)Online publication date: 8-May-2024
    • (2023)MeLPUF: Memory-in-Logic PUF Structures for Low-Overhead IC Authentication2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)10.1109/PAINE58317.2023.10317943(1-7)Online publication date: 24-Oct-2023
    • (2022)Gate-Level Hardware Countermeasure Comparison against Power Analysis AttacksApplied Sciences10.3390/app1205239012:5(2390)Online publication date: 25-Feb-2022
    • (2022)Hardware Moving Target Defenses against Physical AttacksProceedings of the 9th ACM Workshop on Moving Target Defense10.1145/3560828.3564010(25-36)Online publication date: 11-Nov-2022
    • (2022)Hands-On Teaching of Hardware Security for Machine LearningProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530828(455-461)Online publication date: 6-Jun-2022
    • (2022)Guarding Machine Learning Hardware Against Physical Side-channel AttacksACM Journal on Emerging Technologies in Computing Systems10.1145/346537718:3(1-31)Online publication date: 28-Apr-2022
    • (2022)TP-NET: Training Privacy-Preserving Deep Neural Networks under Side-Channel Power Attacks2022 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES54909.2022.00095(439-444)Online publication date: Dec-2022
    • (2021)Enabling energy-efficient DNN training on hybrid GPU-FPGA acceleratorsProceedings of the 35th ACM International Conference on Supercomputing10.1145/3447818.3460371(227-241)Online publication date: 3-Jun-2021
    • (2021)QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection AttacksACM Transactions on Design Automation of Electronic Systems10.1145/344370626:5(1-36)Online publication date: 5-Jun-2021
    • (2021)Power Swapper: Approximate Functional Block Assisted Cryptosystem Security2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739304(101-105)Online publication date: 14-Sep-2021
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