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Supporting multithreading in configurable soft processor cores

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CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 155 - 159

https://doi.org/10.1145/1289881.1289910

Published: 30 September 2007 Publication History

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Abstract

In this paper, we describe the organization and microarchitecture of MT-MB, a configurable implementation of the Xilinx MicroBlaze soft processor that supports multithreading. Using a~suite of synthetic benchmarks, we evaluate five variations of MT-MB and show that multithreading is very effective in hiding the variable latencies associated with custom instructions and custom computational units. Our experimental results show that interleaved and hybrid multithreading achieve speedup factors of 1.10 x to 5.13 x compared to our single-threaded baseline soft processor.

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B. Fort et al., "A Multithreaded Soft Processor for SoPC Area Reduction", Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), pp. 131--142, IEEE, Apr. 24-26, 2006.

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Cited By

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Matthews EGao YShannon L(2020)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM48280.2020.00025(120-128)Online publication date: May-2020
https://doi.org/10.1109/FCCM48280.2020.00025
Shahrouzi SAlkamil APerera D(2020)Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAsIEEE Access10.1109/ACCESS.2020.29948828(91531-91545)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2994882
Li XMaskell D(2019)Time-Multiplexed FPGA Overlay ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/333986124:5(1-19)Online publication date: 23-Jul-2019
https://dl.acm.org/doi/10.1145/3339861
Show More Cited By

Index Terms

Supporting multithreading in configurable soft processor cores
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
      2. Hardware-software codesign

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Published In

CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

September 2007

292 pages

ISBN:9781595938268

DOI:10.1145/1289881

General Chairs:
Taewhan Kim
Seoul National University, South Korea
,
Pascal Sainrat
IRIT - Université de Toulouse, France
,
Program Chairs:
Steven S. Lumetta
University of Illinois at Urbana-Champaign, USA
,
Nacho Navarro
Universitat Politecnica de Catalunya, Spain

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2007

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ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

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Matthews EGao YShannon L(2020)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM48280.2020.00025(120-128)Online publication date: May-2020
https://doi.org/10.1109/FCCM48280.2020.00025
Shahrouzi SAlkamil APerera D(2020)Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAsIEEE Access10.1109/ACCESS.2020.29948828(91531-91545)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2994882
Li XMaskell D(2019)Time-Multiplexed FPGA Overlay ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/333986124:5(1-19)Online publication date: 23-Jul-2019
https://dl.acm.org/doi/10.1145/3339861
Matthews EAguila ZShannon L(2018)Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2018.00010(1-8)Online publication date: Apr-2018
https://doi.org/10.1109/FCCM.2018.00010
Shahrouzi SPerera D(2017)An efficient FPGA-based memory architecture for compute-intensive applications on embedded devices2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)10.1109/PACRIM.2017.8121901(1-8)Online publication date: Aug-2017
https://doi.org/10.1109/PACRIM.2017.8121901
Shahrouzi SPerera D(2017)An efficient embedded multi-ported memory architecture for next-generation FPGAs2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2017.7995263(83-90)Online publication date: Jul-2017
https://doi.org/10.1109/ASAP.2017.7995263
Townsend KAttia OJones PZambreno J(2015)A scalable unsegmented multiport memory for FPGA-based systemsInternational Journal of Reconfigurable Computing10.1155/2015/8262832015(11-11)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1155/2015/826283
Laforest CLi ZO'rourke TLiu MSteffan J(2014)Composing Multi-Ported Memories on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26296297:3(1-23)Online publication date: 3-Sep-2014
https://dl.acm.org/doi/10.1145/2629629
LaForest CSteffan JCompton KHutchings B(2012)OCTAVOProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145731(219-228)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145731
Laforest CLiu MRapati ESteffan JCompton KHutchings B(2012)Multi-ported memories for FPGAs via XORProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145730(209-218)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145730
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