Article

Electromigration and voltage drop aware power grid optimization for power gated ICs

Authors:

Aida Todri,

Shih-Chieh Chang,

Malgorzata Marek-SadowskaAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 391 - 394

https://doi.org/10.1145/1283780.1283866

Published: 27 August 2007 Publication History

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Abstract

Power gating is an efficient technique for reducing leakage power by disconnecting idle blocks from power supply. Gated blocks cause changes in current densities on the grid. Even in DC conditions for some power gating configuration (PGC), current densities in some branches may increase to the extent of violating electromigration (EM) constraints. The existing DC methods optimize the grid under voltage drop (IR) and EM constraints for a single configuration of blocks. We analyze the effects of power gating and develop a grid sizing algorithm to satisfy all reliability constraints for multiple PGCs with only a small increase in area.

References

[1]

X. D. Tan and C. J. R. Shi, "Fast power/ground network optimization based on equivalent circuit modeling," in Proc. Design Automation Conf., 2001.

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[2]

S. Boyd, L. Vandenberghe, A. E. Gamal, and S. Yun, "Design of robust global power and ground networks," in Proc. Int. Symp. Phys. Design, 2001, pp. 60--65.

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[3]

J. Cong, "An interconnect-centric design flow for nanometer technologies," in Proc. IEEE, 2001, vol 89, pp. 487--480.

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[4]

R. L. Boylestad, Introduction to Circuit Analysis, Prentice Hall, 2000.

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Cited By

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Qi ZWang WYu CNiu DWu XJin Z(2024)UnetPro: Combining Attention with Skip Connection in Unet for Efficient IR Drop Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617653(510-515)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617653
Cheng YTodri-Sanial AYang JZhao W(2016)Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing EffectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254326024:11(3310-3322)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2543260
Lee MYi-Chu Liu Wan-Rong Wu Liu C(2012)Peak wake-up current estimation at gate-level with standard library informationProceedings of Technical Program of 2012 VLSI Design, Automation and Test10.1109/VLSI-DAT.2012.6212629(1-4)Online publication date: Apr-2012
https://doi.org/10.1109/VLSI-DAT.2012.6212629

Index Terms

Electromigration and voltage drop aware power grid optimization for power gated ICs
1. Hardware
  1. Hardware validation

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Information & Contributors

Information

Published In

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 August 2007

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ISLPED07

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Qi ZWang WYu CNiu DWu XJin Z(2024)UnetPro: Combining Attention with Skip Connection in Unet for Efficient IR Drop Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617653(510-515)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617653
Cheng YTodri-Sanial AYang JZhao W(2016)Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing EffectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254326024:11(3310-3322)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2543260
Lee MYi-Chu Liu Wan-Rong Wu Liu C(2012)Peak wake-up current estimation at gate-level with standard library informationProceedings of Technical Program of 2012 VLSI Design, Automation and Test10.1109/VLSI-DAT.2012.6212629(1-4)Online publication date: Apr-2012
https://doi.org/10.1109/VLSI-DAT.2012.6212629

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Recommendations

Electromigration study of power-gated grids

Reliability analysis and optimization of power-gated ICs

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI