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Towards a software approach to mitigate voltage emergencies

Authors:

David BrooksAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 123 - 128

https://doi.org/10.1145/1283780.1283808

Published: 27 August 2007 Publication History

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Abstract

Increases in peak current draw and reductions in the operating voltages ofprocessors continue to amplify the importance of dealing with voltage fluctuations in processors. One approach suggested has been to not only react to these fluctuations but also attempt to eliminate future occurrences of these fluctuations by dynamically modifying the executing program. This paper investigates the potential of a very simple dynamic scheme to appreciably reduce the number of run-time voltage emergencies. It shows that we can map many of the voltage emergencies in the execution of the SPEC benchmarks on an aggressive superscalar design to a few static loops, categorize the microarchitectural cause of the emergencies in each important loop through simple observations and a simple priority function, and finally apply straight forward software optimization strategies to mitigate up to 70% of the future voltage swings.

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Cited By

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Tsiokanos IPapadimitriou GGizopoulos DKarakonstantis G(2022)Hardware Level ApproximationsApproximate Computing Techniques10.1007/978-3-030-94705-7_3(43-79)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_3
Papadimitriou GGizopoulos D(2022)Challenges on Unveiling Voltage Margins from the Node to the Datacentre LevelComputing at the EDGE10.1007/978-3-030-74536-3_2(13-49)Online publication date: 20-Sep-2022
https://doi.org/10.1007/978-3-030-74536-3_2
Kalyanam VMahurin EBowman KAbraham J(2021)A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ ProcessorIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.304378656:4(1166-1175)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3043786
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Index Terms

Towards a software approach to mitigate voltage emergencies
1. Hardware
  1. Communication hardware, interfaces and storage

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Information & Contributors

Information

Published In

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 August 2007

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ISLPED07

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Tsiokanos IPapadimitriou GGizopoulos DKarakonstantis G(2022)Hardware Level ApproximationsApproximate Computing Techniques10.1007/978-3-030-94705-7_3(43-79)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_3
Papadimitriou GGizopoulos D(2022)Challenges on Unveiling Voltage Margins from the Node to the Datacentre LevelComputing at the EDGE10.1007/978-3-030-74536-3_2(13-49)Online publication date: 20-Sep-2022
https://doi.org/10.1007/978-3-030-74536-3_2
Kalyanam VMahurin EBowman KAbraham J(2021)A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ ProcessorIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.304378656:4(1166-1175)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3043786
Papadimitriou GChatzidimitriou AGizopoulos DReddi VLeng JSalami BUnsal OKestelman A(2020)Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware MarginsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2020.298981320:2(341-350)Online publication date: Jun-2020
https://doi.org/10.1109/TDMR.2020.2989813
Nikolaou PSazeides Y(2020)Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS48437.2020.00049(296-305)Online publication date: Aug-2020
https://doi.org/10.1109/ISPASS48437.2020.00049
Gizopoulos DPapadimitriou GChatzidimitriou AReddi VSalami BUnsal OKestelman ALeng J(2019)Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2019.8854386(129-134)Online publication date: Jul-2019
https://doi.org/10.1109/IOLTS.2019.8854386
Papadimitriou GChatzidimitriou AGizopoulos D(2019)Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00033(133-146)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00033
Hadjilambrou ZDas SAntoniades MSazeides YOskin MInoue K(2018)Leveraging CPU electromagnetic emanations for voltage noise characterizationProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00053(573-585)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00053
Papadimitriou GChatzidimitriou AKaliorakis MVastakis YGizopoulos D(2018)Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2018.00014(54-63)Online publication date: Apr-2018
https://doi.org/10.1109/ISPASS.2018.00014
Haj-Yahya JMendelson ABen Asher YChattopadhyay AHaj-Yahya JMendelson ABen Asher YChattopadhyay A(2018)Compiler-Directed Energy EfficiencyEnergy Efficient High Performance Processors10.1007/978-981-10-8554-3_4(107-133)Online publication date: 23-Mar-2018
https://doi.org/10.1007/978-981-10-8554-3_4
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Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization

Eliminating voltage emergencies via software-guided code transformations

Automating Stressmark Generation for Testing Processor Voltage Fluctuations