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Optimal redistribution of white space for wire length minimization

Published: 18 January 2005 Publication History

Abstract

Existing floorplanning algorithms compact blocks to the left and bottom. Although the compaction obtains an optimal area, it may not be good to meet other objectives such as minimizing total wire length which is the first-order objective. It is not known in the literature how to place blocks to obtain an optimal wire length. In this paper, we first show that the problem can be formulated as linear programming. Thereafter, instead of using the general but slow linear programming, we propose an efficient min-cost flow based approach to solve it. Our approach guarantees to obtain the minimum of total wire length in polynomial time and meanwhile keep the minimum area by distributing white space smarter for a given floorplan topology. We also show that the approach can be easily extended to handle constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, soft blocks, one-dimensional cluster placement, and bounded net delay, without loss of optimality. Practically, the algorithm is so efficient in that it finishes in less than 0.4 seconds for all MCNC benchmarks of block placement. It is also very effective. Experimental results show we can improve 4.2% of wire length even on very compact floorplans. Thus it provides an ideal way of post-floorplanning (refine floorplanning).

References

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Cited By

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  • (2023)Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323841(1-9)Online publication date: 28-Oct-2023
  • (2020)DREAMPlace 2.0: Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs2020 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC49141.2020.9282573(1-4)Online publication date: 26-Jun-2020
  • (2018)Layout-dependent aging mitigation for critical path timingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201640(153-158)Online publication date: 22-Jan-2018
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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 January 2005

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Cited By

View all
  • (2023)Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323841(1-9)Online publication date: 28-Oct-2023
  • (2020)DREAMPlace 2.0: Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs2020 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC49141.2020.9282573(1-4)Online publication date: 26-Jun-2020
  • (2018)Layout-dependent aging mitigation for critical path timingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201640(153-158)Online publication date: 22-Jan-2018
  • (2018)Layout-dependent aging mitigation for critical path timing2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297298(153-158)Online publication date: Jan-2018
  • (2017)Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.268106436:8(1265-1273)Online publication date: Aug-2017
  • (2017)High Performance Dummy Fill Insertion With Coupling and Uniformity ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.263845236:9(1532-1544)Online publication date: Sep-2017
  • (2015)High performance dummy fill insertion with coupling and uniformity constraintsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744850(1-6)Online publication date: 7-Jun-2015
  • (2014)Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230583133:6(879-892)Online publication date: Jun-2014
  • (2013)3D thermal-aware floorplanner using a MOEA approximationIntegration, the VLSI Journal10.1016/j.vlsi.2012.04.00346:1(10-21)Online publication date: 1-Jan-2013
  • (2012)Block-level 3D IC design with through-silicon-via planning17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164969(335-340)Online publication date: Jan-2012
  • Show More Cited By

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