Article

Implementation of fast CRC calculation

Authors:

Tomas Henriksson,

Dake LiuAuthors Info & Claims

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Pages 563 - 564

https://doi.org/10.1145/1119772.1119892

Published: 21 January 2003 Publication History

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Abstract

CRC is important for error detection in communication systems. With transmission speeds of several Gb/s the high-speed implementation is a bottleneck. A circuit with two parallel calculation units has been implemented in a 0.35 micron process. They use 32 bits and 64 bits parallel input respectively. Chip measurements prove throughput higher than 5.76 Gb/s, which indicates that 10 Gb/s throughput is possible in more modern processes.

References

[1]

T.-B. Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI", IEEE Transactions on Communications, Vol. 40, pp. 653--657, April 1992.

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[2]

R. J. Glaise and X. Jacquart, "Fast CRC Calculation", Proceedings of IEEE International Conference on Computer Design: VLSI in Computers, pp. 602--605, 1993

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Cited By

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Kekely LCabal JKořenek JEbeling WPöschel T(2019)Effective FPGA Architecture for General CRCLectures on Quantum Statistics10.1007/978-3-030-18656-2_16(211-223)Online publication date: 25-Apr-2019
https://doi.org/10.1007/978-3-030-18656-2_16
Cabal JKekely LKorenek J(2018)High-Speed Computation of CRC Codes for FPGAs2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00042(234-237)Online publication date: Dec-2018
https://doi.org/10.1109/FPT.2018.00042
Erazo RCobos CMendoza M(2014)Web services model to snapshot replication over multiple database enginesRevista Facultad de Ingeniería Universidad de Antioquia10.17533/udea.redin.18511(144-157)Online publication date: 17-Feb-2014
https://doi.org/10.17533/udea.redin.18511
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Implementation of fast CRC calculation
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Information

Published In

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

January 2003

865 pages

ISBN:0780376609

DOI:10.1145/1119772

General Chair:
Hiroto Yasuura

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2003

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all

Kekely LCabal JKořenek JEbeling WPöschel T(2019)Effective FPGA Architecture for General CRCLectures on Quantum Statistics10.1007/978-3-030-18656-2_16(211-223)Online publication date: 25-Apr-2019
https://doi.org/10.1007/978-3-030-18656-2_16
Cabal JKekely LKorenek J(2018)High-Speed Computation of CRC Codes for FPGAs2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00042(234-237)Online publication date: Dec-2018
https://doi.org/10.1109/FPT.2018.00042
Erazo RCobos CMendoza M(2014)Web services model to snapshot replication over multiple database enginesRevista Facultad de Ingeniería Universidad de Antioquia10.17533/udea.redin.18511(144-157)Online publication date: 17-Feb-2014
https://doi.org/10.17533/udea.redin.18511
AKAGIC AAMANO H(2013)High-Speed Fully-Adaptable CRC AcceleratorsIEICE Transactions on Information and Systems10.1587/transinf.E96.D.1299E96.D:6(1299-1308)Online publication date: 2013
https://doi.org/10.1587/transinf.E96.D.1299
WU FJIA SMENG QLV SWANG YZHANG D(2013)Improved CRC Calculation Strategies for 64-bit Serial RapidIOIEICE Transactions on Electronics10.1587/transele.E96.C.1330E96.C:10(1330-1338)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.1330
Nagpurwala ASundaresan CChaitanya C(2013)Implementation of HDLC controller design using Verilog HDL2013 International Conference on Electrical, Electronics and System Engineering (ICEESE)10.1109/ICEESE.2013.6895033(7-10)Online publication date: Dec-2013
https://doi.org/10.1109/ICEESE.2013.6895033
Akagić AAmano H(2011)High speed CRC with 64-bit generator polynomial on an FPGAACM SIGARCH Computer Architecture News10.1145/2082156.208217539:4(72-77)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1145/2082156.2082175
Wang JZhang WZhang YWu WChang W(2009)Design and implementation of HDLC procedures based on FPGAProceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication10.5555/1719110.1719189(336-339)Online publication date: 20-Aug-2009
https://dl.acm.org/doi/10.5555/1719110.1719189
Toal CMcLaughlin KSezer SYang X(2009)Design and implementation of a field programmable CRC circuit architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200874117:8(1142-1147)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008741
Supriyanto Budiarto RMurugesan RRamadass S(2009)CRC extension header (CEH): A new model to handle transmission error for IPv6 packets over fiber optic links2009 IEEE Symposium on Industrial Electronics & Applications10.1109/ISIEA.2009.5356384(569-573)Online publication date: Oct-2009
https://doi.org/10.1109/ISIEA.2009.5356384
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