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Branch predictor design and performance estimation for a high performance embedded microprocessor

Published: 21 January 2003 Publication History

Abstract

AE64000 is a 64-bit embedded processor targeting high-end embedded applications such as HDTV, DVD, and 3D graphics. To achieve a higher performance for the AE64000, we design a branch predictor for the processor, and find the optimum parameters for the design through cycle-accurate simulations on SpecINT benchmarks and embedded applications (Dhrystone and Whetstone).In AE64000 branch prediction is complicated by the Instruction Folding Unit (IFU) of the processor front-end. By predicting on a Pre-PC in the IFU rather than using a PC in the pipeline core, we can effectively eliminate branch misprediction penalty on a correct prediction. We have developed the AE64000 simulator to evaluate the performance of the designed branch predictor, and selected the optimum branch predictor configuration by considering cost-effectiveness as well as by analyzing the results generated from AE64000 simulator. The selected branch predictor has been implemented in Verilog and is added to AE64000 pipeline.

References

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S. McFarling, "Combining Branch Predictors", DEC WRL Technical Note TN-36, June 1993
[2]
Brian K. Bray, M. J. Flynn, "Strategies for branch target buffers", Proceedings of the 24th Annual International Symposium on Microarchitecture, September 1991
[3]
T. Y. Yeh, D. Marr, Y. Patt, "Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache", in proceeding of the 1993 International Conference on Supercomputing, 1993
[4]
John L Hennessy, David A Patterson, "Computer Architecture: A Quantitative Approach" 2nd edition, published by Morgan Kaufmann, 1996
[5]
T. Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction", in Proceedings of the 19th Annual ACM/IEEE International Symposium on Computer Architecture, 1992
[6]
The Standard Performance Evaluation Corporation, http://www.specbench.org
  1. Branch predictor design and performance estimation for a high performance embedded microprocessor

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        cover image ACM Conferences
        ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
        January 2003
        865 pages
        ISBN:0780376609
        DOI:10.1145/1119772
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        New York, NY, United States

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        Published: 21 January 2003

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