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Article

PowerViP: Soc power estimation framework at transaction level

Authors:

Eui-Young Chung,

Kyu-Myung Choi,

Jeong-Taek Kong,

Soo-Kwan EoAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 551 - 558

https://doi.org/10.1145/1118299.1118431

Published: 24 January 2006 Publication History

Abstract

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design.

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Cited By

Genser ABachmann CSteger CWeiss RHaid J(2019)A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management10.1007/978-3-662-58834-5_4(59-78)Online publication date: 23-Feb-2019
https://doi.org/10.1007/978-3-662-58834-5_4
Darwish AEl-Moursy MDessouky MDarwish AEl-Moursy MDessouky M(2019)Power Modeling and CharacterizationTransaction-Level Power Modeling10.1007/978-3-030-24827-7_3(47-57)Online publication date: 1-Aug-2019
https://doi.org/10.1007/978-3-030-24827-7_3
Lee DGerstlauer A(2018)Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPsACM Transactions on Design Automation of Electronic Systems10.1145/317786523:3(1-25)Online publication date: 23-Feb-2018
https://dl.acm.org/doi/10.1145/3177865
Show More Cited By

Index Terms

PowerViP: Soc power estimation framework at transaction level
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press

Publication History

Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Citations

Cited By

Genser ABachmann CSteger CWeiss RHaid J(2019)A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management10.1007/978-3-662-58834-5_4(59-78)Online publication date: 23-Feb-2019
https://doi.org/10.1007/978-3-662-58834-5_4
Darwish AEl-Moursy MDessouky MDarwish AEl-Moursy MDessouky M(2019)Power Modeling and CharacterizationTransaction-Level Power Modeling10.1007/978-3-030-24827-7_3(47-57)Online publication date: 1-Aug-2019
https://doi.org/10.1007/978-3-030-24827-7_3
Lee DGerstlauer A(2018)Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPsACM Transactions on Design Automation of Electronic Systems10.1145/317786523:3(1-25)Online publication date: 23-Feb-2018
https://dl.acm.org/doi/10.1145/3177865
Chen CShieh MLu JHuang HChen Y(2017)Content-aware line-based power modeling methodology for image signal processor2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226075(346-350)Online publication date: Sep-2017
https://doi.org/10.1109/SOCC.2017.8226075
Eriksrod JKjelgard KTommer MBurkhart JLande T(2017)Bi-static environmental SAR radar imager2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124979(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/NORCHIP.2017.8124979
Sundaram SHe WSambamurthy SGrenat ALiepe SNaffziger S(2016)Unified Power Frequency Model FrameworkProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934605(174-179)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934605
Lee DKim THan KHoskote YJohn LGerstlauer AMarculescu DLiu F(2015)Learning-Based Power Modeling of System-Level Black-Box IPsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840937(847-853)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840937
Lee DJohn LGerstlauer ANebel WAtienza D(2015)Dynamic power and performance back-annotation for fast and accurate functional hardware simulationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757074(1126-1131)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757074
Oliveira HBrito AMelcher EBucher HAraújo JDuenha LAzevedo Rde Lima RCunha APlett Cde Oliveira W(2015)Power-Aware Design of Electronic System Level using Interoperation of Hybrid and Distributed SimulationsProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801023(1-7)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2800986.2801023
Lee DKim THan KHoskote YJohn LGerstlauer A(2015)Learning-based power modeling of system-level black-box IPs2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372659(847-853)Online publication date: Nov-2015
https://doi.org/10.1109/ICCAD.2015.7372659
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