[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/1118299.1118439acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
Article

Reusable component IP design using refinement-based design environment

Published: 24 January 2006 Publication History

Abstract

We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the component designers describe mainly the computation part of the component, and the system designer can construct the communication part by using our refinement-based design environment. Moreover, we introduced a concept of the Communication Architecture Template Tree (CATree), which helps IP designers to effectively separate computation and communication for a system function. We confirmed that this approach is effective by applying it to a H.264 decoder design.

References

[1]
Michael Keating, Pierre Bricaud, "Reuse methodology manual", Kluwer academic publisher, 2002
[2]
Y.-T. Hwang and S.-C. Lin, "Automatic protocol translation and template based interface synthesis for IP reuse in SoC", Proc of 10th ASP-DAC, pp. 565--568, Dec. 2004
[3]
K. Keutzer, S. Malik, et. al., "System-level design: Orthogonalization of concerns and platform-based design", Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vo119, No. 12, pp. 1523--1542, Dec. 2000.
[4]
VSI Alliance On-Chip Bus Development Working Group, "OCB 2.0", Apr. 2001
[5]
Sonics Inc. "Open core protocol specification 1.0", 2000
[6]
W. Cesario, D. Lyonnard, G Nicolescu, Y. Paviot, S. Yoo, A. Jerraya, "Multiprocessor SoC Platforms: A Component Based Design Approach", IEEE Design & Test of Computers, pp. 52--63, Nov. 2002,
[7]
F. Gharalli, D. Lyonnard, S. Meftali, F. Rousseau, A. A. Jerraya, "Unifying memory and processor wrapper architecture in multiprocessor SoC design", proc of ISSS'02, pp. 26--31, Oct. 2002.
[8]
S. Abdi, D. Gajski, "Automatic generation of equivalent architecture model from functional specification", Proc. of42th DAC, pp. 608--613, June, 2004

Cited By

View all
  • (2015)Configurable hardware components generator in Python2015 4th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2015.7181876(96-99)Online publication date: Jun-2015
  • (2009)VLSI Implementation of a VC-1 Main Profile Decoder for HD Video ApplicationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.279E92-A:1(279-290)Online publication date: 2009
  • (2009)A mixed-level virtual prototyping environment for SystemC-based design methodologyMicroelectronics Journal10.1016/j.mejo.2008.05.01040:7(1082-1093)Online publication date: 1-Jul-2009
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press

Publication History

Published: 24 January 2006

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 22 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2015)Configurable hardware components generator in Python2015 4th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2015.7181876(96-99)Online publication date: Jun-2015
  • (2009)VLSI Implementation of a VC-1 Main Profile Decoder for HD Video ApplicationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.279E92-A:1(279-290)Online publication date: 2009
  • (2009)A mixed-level virtual prototyping environment for SystemC-based design methodologyMicroelectronics Journal10.1016/j.mejo.2008.05.01040:7(1082-1093)Online publication date: 1-Jul-2009
  • (2008)RTL generation of channel architecture templates for a template-based SoC design flow2008 Forum on Specification, Verification and Design Languages10.1109/FDL.2008.4641460(251-252)Online publication date: Sep-2008
  • (2007)Service dependency graph for HW/SW interfaces modeling: The motion-JPEG case study2007 7th International Conference on ASIC10.1109/ICASIC.2007.4415784(930-933)Online publication date: Oct-2007
  • (2006)A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design EnvironmentProceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping10.1109/RSP.2006.3(63-68)Online publication date: 14-Jun-2006
  • (2006)Implementation of a H.264 decoder with Template-based Communication RefinementAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems10.1109/APCCAS.2006.342052(570-573)Online publication date: Dec-2006

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media