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Energy-efficient motion estimation using error-tolerance

Published: 04 October 2006 Publication History

Abstract

Presented is an energy-efficient motion estimation architecture using error-tolerance. The technique employs overscaling of the supply voltage (voltage overscaling (VOS)) to reduce power at the expense of timing errors, which are then corrected using algorithmic noise-tolerance (ANT) techniques. Referred to as input subsampled replica ANT (ISR-ANT), the proposed technique incorporates an input subsampled replica of the main sum of absolute difference (MSAD) block for obtaining the motion vectors in the presence of errors induced by VOS. Simulations show that the proposed technique can save up to 60% power over an optimal error-free present day system in a 130nm CMOS technology. Power savings increase to 79% in a 45nm predictive process technology.

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    cover image ACM Conferences
    ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design
    October 2006
    446 pages
    ISBN:1595934626
    DOI:10.1145/1165573
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 October 2006

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    Author Tags

    1. low-power
    2. noise-tolerance

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    ISLPED06
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    ISLPED06: International Symposium on Low Power Electronics and Design
    October 4 - 6, 2006
    Bavaria, Tegernsee, Germany

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    • (2023)A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC60832.2023.00031(154-159)Online publication date: 18-Dec-2023
    • (2022)Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-LoopIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2021.305922932:1(398-410)Online publication date: Jan-2022
    • (2021)Comparison and extension of high performance adders for hybrid and error tolerant applicationsJournal of Ambient Intelligence and Humanized Computing10.1007/s12652-021-03574-2Online publication date: 3-Nov-2021
    • (2019)On the Efficiency of Voltage Overscaling under Temperature and Aging EffectsIEEE Transactions on Computers10.1109/TC.2019.2916869(1-1)Online publication date: 2019
    • (2019)High Speed Low Power Radix 4 Approximate Booth Multiplier2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)10.1109/IEMENTech48150.2019.8981022(1-4)Online publication date: Aug-2019
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    • (2018)A promising power-saving technique: Approximate computing2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)10.1109/ISCAIE.2018.8405486(285-290)Online publication date: Apr-2018
    • (2018)Approximate Multi-Accelerator Tiled Architecture for Energy-Efficient Motion EstimationApproximate Circuits10.1007/978-3-319-99322-5_12(249-268)Online publication date: 6-Dec-2018
    • (2017)Embracing approximate computing for energy-efficient motion estimation in high efficiency video codingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130706(1388-1393)Online publication date: 27-Mar-2017
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