Article

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

Authors:

Bhaskar Chatterjee,

Manoj Sachdev,

Ram KrishnamurthyAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 248 - 251

https://doi.org/10.1145/1013235.1013298

Published: 09 August 2004 Publication History

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Abstract

In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180nm-65nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

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B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy and S. Borkar, "Effectiveness and Scaling Trends of Leakage Control Techniques for Sub-130nm CMOS Technologies," Proc. of ISLPED, pp. 122--127, 2003.

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Cited By

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Thangaraj CAlkan CChen T(2010)Rapid design space exploration using legacy design data and technology scaling trendIntegration, the VLSI Journal10.1016/j.vlsi.2009.11.00243:2(202-219)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1016/j.vlsi.2009.11.002
McIver JClark L(2005)Reducing radiation-hardened DigitalCircuit power consumptionIEEE Transactions on Nuclear Science10.1109/TNS.2005.86108252:6(2503-2509)Online publication date: Dec-2005
https://doi.org/10.1109/TNS.2005.861082

Index Terms

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information

Published In

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 August 2004

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ISLPED04

Sponsor:

ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Thangaraj CAlkan CChen T(2010)Rapid design space exploration using legacy design data and technology scaling trendIntegration, the VLSI Journal10.1016/j.vlsi.2009.11.00243:2(202-219)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1016/j.vlsi.2009.11.002
McIver JClark L(2005)Reducing radiation-hardened DigitalCircuit power consumptionIEEE Transactions on Nuclear Science10.1109/TNS.2005.86108252:6(2503-2509)Online publication date: Dec-2005
https://doi.org/10.1109/TNS.2005.861082

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An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach

PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies

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