Article

Architecting voltage islands in core-based system-on-a-chip designs

Authors:

Jingcao Hu,

Youngsoo Shin,

Nagu Dhanwada,

Radu MarculescuAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 180 - 185

https://doi.org/10.1145/1013235.1013283

Published: 09 August 2004 Publication History

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Abstract

Voltage islands enable core-level power optimization for System-on-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves island partition creation, voltage level assignment and floorplanning. The task of island partition creation and level assignment have to be done simultaneously in a floorplanning context due to the physical constraints involved in the design process. This leads to a floorplanning problem formulation that is very different from the traditional floorplanning for ASIC-style design.In this paper, we define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Application of the proposed algorithm to a few benchmark and industrial examples is demonstrated using a prototype tool. Results show power savings of 14%--28%, depending on the constraints imposed on the number of voltage islands and other physical-level parameters.

References

[1]

R. A. Bergamaschi, Y. Shin, N. Dhanwada, S. Bhattacharya, W. E. Dougherty, I. Nair, J. Darringer, and S. Paliwal, "SEAS: A system for early analysis of SoCs," in Proc. Int'l Conf. on Hardware/Software Codesign and System Synthesis, Oct. 2003, pp. 150--155.

Digital Library

Google Scholar

[2]

M. Pedram and J. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, 2002.

Digital Library

Google Scholar

[3]

D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn, "Managing power and performance for System-on-Chip designs using voltage islands," in Proc. Int'l Conf. on Computer Aided Design, Nov. 2002, pp. 195--202.

Digital Library

Google Scholar

[4]

A. B. Kahng, "Classical floorplanning harmful?," in Proc. Int'l Symp. on Physical Design, Apr. 2000, pp. 207--213.

Digital Library

Google Scholar

[5]

F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. on VLSI Systems, vol. 2, no. 4, pp. 446--455, Dec. 1994.

Digital Library

Google Scholar

[6]

X. Tang and D. F. Wong, "FAST-SP: a fast algorithm for block placement based on sequence pair," in Proc. Asia South Pacific Design Automat. Conf., Jan. 2001, pp. 512--526.

Digital Library

Google Scholar

[7]

H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair," IEEE Trans. on Computer-Aided Design, vol. 15, no. 12, pp. 1518--1524, Dec. 1996.

Digital Library

Google Scholar

[8]

X. Tang and D. F. Wong, "Floorplanning with alignment and performance constraints," in Proc. Design Automat. Conf., June 2002, pp. 848--853.

Digital Library

Google Scholar

[9]

IBM Corp., "IBM platform-based design kit," http://www-3.ibm.com/chips/products/asics/methodology/design_kit.html.

Google Scholar

Cited By

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Shanthi JRani DRajaram S(2022)A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip designMicroelectronics Journal10.1016/j.mejo.2022.105361121(105361)Online publication date: Mar-2022
https://doi.org/10.1016/j.mejo.2022.105361
Huang AWang DZhao RZhang Q(2019)Au-IdProceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies10.1145/33289193:2(1-26)Online publication date: 21-Jun-2019
https://dl.acm.org/doi/10.1145/3328919
Venkatnarayan RShahzad M(2019)Enhancing Indoor Inertial Odometry with WiFiProceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies10.1145/33289183:2(1-27)Online publication date: 21-Jun-2019
https://dl.acm.org/doi/10.1145/3328918
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Index Terms

Architecting voltage islands in core-based system-on-a-chip designs
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Information

Published In

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 August 2004

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ISLPED04

Sponsor:

ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Shanthi JRani DRajaram S(2022)A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip designMicroelectronics Journal10.1016/j.mejo.2022.105361121(105361)Online publication date: Mar-2022
https://doi.org/10.1016/j.mejo.2022.105361
Huang AWang DZhao RZhang Q(2019)Au-IdProceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies10.1145/33289193:2(1-26)Online publication date: 21-Jun-2019
https://dl.acm.org/doi/10.1145/3328919
Venkatnarayan RShahzad M(2019)Enhancing Indoor Inertial Odometry with WiFiProceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies10.1145/33289183:2(1-27)Online publication date: 21-Jun-2019
https://dl.acm.org/doi/10.1145/3328918
Jahier Pagliari DDurand YCoriat DBeigne EMacii EPoncino M(2019)Fine-Grain Back Biasing for the Design of Energy-Quality Scalable OperatorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283440038:6(1042-1055)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834400
Balasubramanian SPanchanathan AChokkalingam BPadmanaban SLeonowicz Z(2018)Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline ConstraintsElectronics10.3390/electronics71103257:11(325)Online publication date: 15-Nov-2018
https://doi.org/10.3390/electronics7110325
Lin JHuang CYang J(2018)Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342221(1339-1344)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342221
Deng LZhao YWang S(2018)Modified Adaptive Differential Evolution Algorithm for Test Scheduling of Multi-Core SOC Based on DVS and MVI2018 Eighth International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC)10.1109/IMCCC.2018.00125(569-574)Online publication date: Jul-2018
https://doi.org/10.1109/IMCCC.2018.00125
Pagliari DDurand YCoriat DMolnos ABeigne EMacii EPoncino M(2017)A methodology for the design of dynamic accuracy operators by runtime back biasProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130654(1165-1170)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130654
Pagliari DDurand YCoriat DMolnos ABeigne EMacii EPoncino M(2017)A methodology for the design of dynamic accuracy operators by runtime back biasDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927165(1165-1170)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927165
Zhang QLai LGottscho MGupta PFanucci LTeich J(2016)Multi-story power distribution networks for GPUsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971913(451-456)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971913
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